157 lines
7.4 KiB
LLVM
157 lines
7.4 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-- -mcpu=bonaire -loop-reduce < %s | FileCheck -check-prefix=OPT %s
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; Test that loops with different maximum offsets for different address
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; spaces are correctly handled.
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_i32(
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; OPT: {{^}}.lr.ph:
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; OPT: %lsr.iv2 = phi i8 addrspace(1)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(1)* %lsr.iv2, i64 4095
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; OPT: load i8, i8 addrspace(1)* %scevgep4, align 1
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define amdgpu_kernel void @test_global_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(1)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
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.lr.ph.preheader: ; preds = %bb
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br label %.lr.ph
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._crit_edge.loopexit: ; preds = %.lr.ph
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br label %._crit_edge
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._crit_edge: ; preds = %._crit_edge.loopexit, %bb
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ret void
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.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
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%tmp1 = add nuw nsw i64 %indvars.iv, 4095
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%tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg1, i64 %tmp1
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%tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1
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%tmp4 = sext i8 %tmp3 to i32
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
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%tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
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%tmp7 = add nsw i32 %tmp6, %tmp4
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store i32 %tmp7, i32 addrspace(1)* %tmp5, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
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}
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; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_p1_i32(
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; OPT: {{^}}.lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i8, i8 addrspace(1)* %arg1, i64 4096
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; OPT: br label %.lr.ph
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; OPT: {{^}}.lr.ph:
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; OPT: %lsr.iv3 = phi i8 addrspace(1)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(1)* %lsr.iv3, i64 1
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define amdgpu_kernel void @test_global_addressing_loop_uniform_index_max_offset_p1_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(1)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
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.lr.ph.preheader: ; preds = %bb
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br label %.lr.ph
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._crit_edge.loopexit: ; preds = %.lr.ph
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br label %._crit_edge
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._crit_edge: ; preds = %._crit_edge.loopexit, %bb
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ret void
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.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
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%tmp1 = add nuw nsw i64 %indvars.iv, 4096
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%tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg1, i64 %tmp1
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%tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1
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%tmp4 = sext i8 %tmp3 to i32
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
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%tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
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%tmp7 = add nsw i32 %tmp6, %tmp4
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store i32 %tmp7, i32 addrspace(1)* %tmp5, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
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}
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; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_i32(
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; OPT: {{^}}.lr.ph
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; OPT: %lsr.iv2 = phi i8 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(3)* %lsr.iv2, i32 65535
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; OPT: %tmp4 = load i8, i8 addrspace(3)* %scevgep4, align 1
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define amdgpu_kernel void @test_local_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
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.lr.ph.preheader: ; preds = %bb
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br label %.lr.ph
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._crit_edge.loopexit: ; preds = %.lr.ph
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br label %._crit_edge
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._crit_edge: ; preds = %._crit_edge.loopexit, %bb
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ret void
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.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
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%tmp1 = add nuw nsw i64 %indvars.iv, 65535
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%tmp2 = trunc i64 %tmp1 to i32
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%tmp3 = getelementptr inbounds i8, i8 addrspace(3)* %arg1, i32 %tmp2
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%tmp4 = load i8, i8 addrspace(3)* %tmp3, align 1
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%tmp5 = sext i8 %tmp4 to i32
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%tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
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%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
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%tmp8 = add nsw i32 %tmp7, %tmp5
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store i32 %tmp8, i32 addrspace(1)* %tmp6, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
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}
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; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_p1_i32(
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; OPT: {{^}}.lr.ph.preheader:
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; OPT: %scevgep2 = getelementptr i8, i8 addrspace(3)* %arg1, i32 65536
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; OPT: br label %.lr.ph
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; OPT: {{^}}.lr.ph:
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; OPT: %lsr.iv3 = phi i8 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(3)* %lsr.iv3, i32 1
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define amdgpu_kernel void @test_local_addressing_loop_uniform_index_max_offset_p1_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
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.lr.ph.preheader: ; preds = %bb
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br label %.lr.ph
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._crit_edge.loopexit: ; preds = %.lr.ph
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br label %._crit_edge
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._crit_edge: ; preds = %._crit_edge.loopexit, %bb
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ret void
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.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
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%tmp1 = add nuw nsw i64 %indvars.iv, 65536
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%tmp2 = trunc i64 %tmp1 to i32
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%tmp3 = getelementptr inbounds i8, i8 addrspace(3)* %arg1, i32 %tmp2
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%tmp4 = load i8, i8 addrspace(3)* %tmp3, align 1
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%tmp5 = sext i8 %tmp4 to i32
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%tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
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%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
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%tmp8 = add nsw i32 %tmp7, %tmp5
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store i32 %tmp8, i32 addrspace(1)* %tmp6, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hawaii" "unsafe-fp-math"="false" "use-soft-float"="false" }
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