163 lines
6.6 KiB
LLVM
163 lines
6.6 KiB
LLVM
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1102 < %s | FileCheck -check-prefix=GCN %s
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; There aren't any stack objects, but we still enable the
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; private_segment_wavefront_offset to get to 16, and the workgroup ID
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; is in s14.
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; private_segment_buffer + workgroup_id_x = 5, + 11 padding
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; GCN-LABEL: {{^}}minimal_kernel_inputs:
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; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15
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; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
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; GCN: .amdhsa_kernel minimal_kernel_inputs
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; GCN: .amdhsa_user_sgpr_count 15
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GCN-NEXT: .amdhsa_wavefront_size32 1
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; GCN-NEXT: .amdhsa_enable_private_segment 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
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define amdgpu_kernel void @minimal_kernel_inputs() {
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}minimal_kernel_inputs_with_stack:
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; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15
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; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
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; GCN: .amdhsa_kernel minimal_kernel_inputs
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; GCN: .amdhsa_user_sgpr_count 15
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GCN-NEXT: .amdhsa_wavefront_size32 1
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; GCN-NEXT: .amdhsa_enable_private_segment 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
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define amdgpu_kernel void @minimal_kernel_inputs_with_stack() {
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%alloca = alloca i32, addrspace(5)
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id, i32 addrspace(1)* undef
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store volatile i32 0, i32 addrspace(5)* %alloca
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ret void
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}
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; GCN-LABEL: {{^}}queue_ptr:
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; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
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; GCN: v_mov_b32_e32 [[V:v[0-9]+]], s15
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; GCN-NEXT: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V]], off
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; GCN: .amdhsa_kernel queue_ptr
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; GCN: .amdhsa_user_sgpr_count 15
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1
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; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GCN-NEXT: .amdhsa_wavefront_size32 1
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; GCN-NEXT: .amdhsa_enable_private_segment 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 15
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define amdgpu_kernel void @queue_ptr() {
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%queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
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%load = load volatile i8, i8 addrspace(4)* %queue.ptr
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}all_inputs:
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; GCN: v_mov_b32_e32 [[V_X:v[0-9]+]], s13
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; GCN: v_mov_b32_e32 [[V_Y:v[0-9]+]], s14
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; GCN: v_mov_b32_e32 [[V_Z:v[0-9]+]], s15
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; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[0:1]
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; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[2:3]
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; GCN: global_load_u8 v{{[0-9]+}}, v{{[0-9]+}}, s[4:5]
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; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_LO:[0-9]+]], s6
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; GCN-DAG: v_mov_b32_e32 v[[DISPATCH_HI:[0-9]+]], s7
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; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_X]], off
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; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Y]], off
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; GCN: global_store_b32 v{{\[[0-9]+:[0-9]+\]}}, [[V_Z]], off
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; GCN: global_store_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[DISPATCH_LO]]:[[DISPATCH_HI]]{{\]}}, off
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; GCN: .amdhsa_kernel all_inputs
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; GCN: .amdhsa_user_sgpr_count 13
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
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; GCN-NEXT: .amdhsa_user_sgpr_queue_ptr 1
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; GCN-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
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; GCN-NEXT: .amdhsa_user_sgpr_dispatch_id 1
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; GCN-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GCN-NEXT: .amdhsa_wavefront_size32 1
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; GCN-NEXT: .amdhsa_enable_private_segment 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
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; GCN-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GCN-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GCN: ; COMPUTE_PGM_RSRC2:USER_SGPR: 13
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define amdgpu_kernel void @all_inputs() {
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%alloca = alloca i32, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %alloca
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%dispatch.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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%load.dispatch = load volatile i8, i8 addrspace(4)* %dispatch.ptr
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%queue.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
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%load.queue = load volatile i8, i8 addrspace(4)* %queue.ptr
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%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%load.implicitarg = load volatile i8, i8 addrspace(4)* %implicitarg.ptr
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%id.x = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id.x, i32 addrspace(1)* undef
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%id.y = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %id.y, i32 addrspace(1)* undef
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%id.z = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %id.z, i32 addrspace(1)* undef
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%dispatch.id = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %dispatch.id, i64 addrspace(1)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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declare align 4 i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
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declare align 4 i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
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declare align 4 i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
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declare align 4 i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
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declare i64 @llvm.amdgcn.dispatch.id() #0
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attributes #0 = { nounwind readnone speculatable willreturn }
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