179 lines
4.8 KiB
LLVM
179 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Test that we turn (sra (shl X, 32), 32-C) into (slli (sext.w X), C)
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define i64 @test1(i64 %a) nounwind {
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; RV64I-LABEL: test1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srai a0, a0, 30
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; RV64I-NEXT: ret
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%1 = shl i64 %a, 32
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%2 = ashr i64 %1, 30
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ret i64 %2
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}
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define i64 @test2(i32 signext %a) nounwind {
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; RV64I-LABEL: test2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srai a0, a0, 29
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; RV64I-NEXT: ret
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 32
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%3 = ashr i64 %2, 29
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ret i64 %3
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}
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define i64 @test3(i32* %a) nounwind {
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; RV64I-LABEL: test3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srai a0, a0, 28
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; RV64I-NEXT: ret
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%1 = load i32, i32* %a
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%2 = zext i32 %1 to i64
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%3 = shl i64 %2, 32
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%4 = ashr i64 %3, 28
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ret i64 %4
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}
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define i64 @test4(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: test4:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srai a0, a0, 2
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; RV64I-NEXT: ret
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%1 = add i32 %a, %b
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%2 = zext i32 %1 to i64
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%3 = shl i64 %2, 32
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%4 = ashr i64 %3, 2
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ret i64 %4
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}
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define i64 @test5(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: test5:
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; RV64I: # %bb.0:
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srai a0, a0, 1
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; RV64I-NEXT: ret
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%1 = xor i32 %a, %b
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%2 = zext i32 %1 to i64
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%3 = shl i64 %2, 32
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%4 = ashr i64 %3, 1
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ret i64 %4
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}
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define i64 @test6(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: test6:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sllw a0, a0, a1
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srai a0, a0, 16
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; RV64I-NEXT: ret
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%1 = shl i32 %a, %b
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%2 = zext i32 %1 to i64
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%3 = shl i64 %2, 32
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%4 = ashr i64 %3, 16
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ret i64 %4
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}
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; The ashr+add+shl is canonical IR from InstCombine for
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; (sext (add (trunc X to i32), 1) to i32).
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; That can be implemented as addiw make sure we recover it.
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define i64 @test7(i32* %0, i64 %1) {
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; RV64I-LABEL: test7:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a1, 32
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; RV64I-NEXT: li a1, 1
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: srai a0, a0, 32
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; RV64I-NEXT: ret
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%3 = shl i64 %1, 32
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%4 = add i64 %3, 4294967296
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%5 = ashr exact i64 %4, 32
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ret i64 %5
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}
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; The ashr+add+shl is canonical IR from InstCombine for
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; (sext (sub 1, (trunc X to i32)) to i32).
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; That can be implemented as (li 1)+subw make sure we recover it.
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define i64 @test8(i32* %0, i64 %1) {
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; RV64I-LABEL: test8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a1, 32
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; RV64I-NEXT: li a1, 1
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: srai a0, a0, 32
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; RV64I-NEXT: ret
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%3 = mul i64 %1, -4294967296
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%4 = add i64 %3, 4294967296
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%5 = ashr exact i64 %4, 32
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ret i64 %5
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}
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; The gep is here to introduce a shl by 2 after the ashr that will get folded
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; and make this harder to recover.
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define signext i32 @test9(i32* %0, i64 %1) {
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; RV64I-LABEL: test9:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: lui a2, 4097
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; RV64I-NEXT: slli a2, a2, 20
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; RV64I-NEXT: add a1, a1, a2
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; RV64I-NEXT: srai a1, a1, 30
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: ret
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%3 = shl i64 %1, 32
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%4 = add i64 %3, 17596481011712 ; 4097 << 32
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%5 = ashr exact i64 %4, 32
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%6 = getelementptr inbounds i32, i32* %0, i64 %5
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%7 = load i32, i32* %6, align 4
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ret i32 %7
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}
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; The gep is here to introduce a shl by 2 after the ashr that will get folded
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; and make this harder to recover.
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define signext i32 @test10(i32* %0, i64 %1) {
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; RV64I-LABEL: test10:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: lui a2, 30141
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; RV64I-NEXT: addiw a2, a2, -747
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; RV64I-NEXT: slli a2, a2, 32
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; RV64I-NEXT: sub a1, a2, a1
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; RV64I-NEXT: srai a1, a1, 30
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: ret
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%3 = mul i64 %1, -4294967296
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%4 = add i64 %3, 530242871224172544 ; 123456789 << 32
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%5 = ashr exact i64 %4, 32
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%6 = getelementptr inbounds i32, i32* %0, i64 %5
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%7 = load i32, i32* %6, align 4
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ret i32 %7
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}
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define i64 @test11(i32* %0, i64 %1) {
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; RV64I-LABEL: test11:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a1, 32
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; RV64I-NEXT: li a1, -1
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; RV64I-NEXT: slli a1, a1, 63
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; RV64I-NEXT: sub a0, a1, a0
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; RV64I-NEXT: srai a0, a0, 32
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; RV64I-NEXT: ret
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%3 = mul i64 %1, -4294967296
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%4 = add i64 %3, 9223372036854775808 ;0x8000'0000'0000'0000
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%5 = ashr exact i64 %4, 32
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ret i64 %5
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}
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