Craig Topper d7de7ac370 [X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models ... Based on uops.info these should have 5 cycle latency as they did on Haswell/Broadwell. I have no additional internal information from Intel. This was also shown as a discrepancy in the spreadsheet that was sent with an early llvm-dev post about llvm-exegesis. It also matches Agner Fog. Differential Revision: https://reviews.llvm.org/D74357		2020-02-11 11:24:25 -08:00
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AArch64	[MCA] Fix test cases (NFC)	2019-11-22 16:19:58 -06:00
ARM	[ARM][Thumb2] Fix ADD/SUB invalid writes to SP	2020-01-14 11:47:19 +00:00
SystemZ	[MCA] Show aggregate over Average Wait times for the whole snippet (PR43219)	2019-10-10 14:46:21 +00:00
X86	[X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models	2020-02-11 11:24:25 -08:00
invalid_input_file_name.test	Replace unused output filenames with /dev/null in tests	2018-07-02 18:16:44 +00:00
lit.local.cfg	[lit] Delete empty lines at the end of lit.local.cfg NFC	2019-06-17 09:51:07 +00:00