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llvm-project/llvm/lib/CodeGen/SelectionDAG
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Craig Topper dcfc1fd26f [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. 
If we have a variable shift amount and the demanded mask has leading
zeros, we can propagate those leading zeros to not demand those bits
from operand 0. This can allow zero_extend/sign_extend to become
any_extend. This pattern can occur due to C integer promotion rules.

This transform is already done by InstCombineSimplifyDemanded.cpp where
sign_extend can be turned into zero_extend for example.

Reviewed By: spatel, foad

Differential Revision: https://reviews.llvm.org/D121833
 		2022-07-14 16:10:14 -07:00
..
CMakeLists.txt
…
DAGCombiner.cpp [DAG] SimplifyDemandedVectorElts - adjust demanded elements for selection mask for known zero results 2022-07-13 17:36:05 +01:00
FastISel.cpp [FastISel] Fix load folding for registers with fixups 2022-05-16 10:25:25 +02:00
FunctionLoweringInfo.cpp [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf 2022-05-19 11:23:13 +01:00
InstrEmitter.cpp [SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources. 2022-06-16 14:55:14 -07:00
InstrEmitter.h [DebugInfo][InstrRef] Avoid a crash from mixed variable location modes 2022-04-06 11:55:38 +01:00
LegalizeDAG.cpp Promote bf16 to f32 when the target doesn't support it 2022-06-15 12:56:31 +02:00
LegalizeFloatTypes.cpp [stackmaps] Start legalizing live variable operands 2022-07-06 14:01:54 +01:00
LegalizeIntegerTypes.cpp [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal 2022-07-07 09:33:54 +00:00
LegalizeTypes.cpp [LegalizeTypes] Fix bug in expensive checks verification 2022-05-26 13:13:32 -07:00
LegalizeTypes.h [stackmaps] Start legalizing live variable operands 2022-07-06 14:01:54 +01:00
LegalizeTypesGeneric.cpp [SelectionDAG][VP] Add splitting support for VP_MERGE 2022-01-25 10:33:23 +00:00
LegalizeVectorOps.cpp [RISCV][VP] Add basic RVV codegen for vp.fcmp 2022-04-07 09:16:07 +01:00
LegalizeVectorTypes.cpp [AArc64] Legalisation of compares and truncates of nxv1i1 types. 2022-07-07 07:39:27 +00:00
ResourcePriorityQueue.cpp Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options 2022-06-05 00:31:44 -07:00
SDNodeDbgValue.h Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
ScheduleDAGFast.cpp [AMDGPU] Check for CopyToReg PhysReg clobbers in pre-RA-sched 2022-06-30 09:18:04 -07:00
ScheduleDAGRRList.cpp [AMDGPU] Check for CopyToReg PhysReg clobbers in pre-RA-sched 2022-06-30 09:18:04 -07:00
ScheduleDAGSDNodes.cpp [DebugInfo][InstrRef] Avoid a crash from mixed variable location modes 2022-04-06 11:55:38 +01:00
ScheduleDAGSDNodes.h [CodeGen] Use default member initialization (NFC) 2022-01-30 12:32:51 -08:00
ScheduleDAGVLIW.cpp Cleanup includes: DebugInfo & CodeGen 2022-03-12 17:26:40 +01:00
SelectionDAG.cpp [RISCV] Exploit fact that vscale is always power of two to replace urem sequence 2022-07-13 10:54:47 -07:00
SelectionDAGAddressAnalysis.cpp [llvm] Don't use Optional::hasValue (NFC) 2022-06-20 10:38:12 -07:00
SelectionDAGBuilder.cpp [llvm] Use value instead of getValue (NFC) 2022-07-13 23:11:56 -07:00
SelectionDAGBuilder.h [IR] Remove support for insertvalue constant expression 2022-07-04 09:27:22 +02:00
SelectionDAGDumper.cpp [stackmaps] Start legalizing live variable operands 2022-07-06 14:01:54 +01:00
SelectionDAGISel.cpp [stackmaps] Start legalizing live variable operands 2022-07-06 14:01:54 +01:00
SelectionDAGPrinter.cpp Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if" 2022-04-06 20:32:53 +03:00
SelectionDAGTargetInfo.cpp
…
StatepointLowering.cpp [llvm] Use value instead of getValue (NFC) 2022-07-13 23:11:56 -07:00
StatepointLowering.h
…
TargetLowering.cpp [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount. 2022-07-14 16:10:14 -07:00