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AsmParser
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[RISCV] Implement support for the Zicbop extension
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2022-06-28 12:43:26 +01:00 |
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Disassembler
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Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
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2022-05-15 08:44:58 +08:00 |
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MCTargetDesc
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[CodeGen] Move instruction predicate verification to emitInstruction
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2022-07-14 09:33:28 +01:00 |
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TargetInfo
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CMakeLists.txt
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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RISCV.h
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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RISCV.td
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[RISCV] Make TuneSiFive7 depend on TuneNoDefaultUnroll instead of listing it for every SiFive7 CPU
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2022-07-14 15:57:30 -07:00 |
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RISCVAsmPrinter.cpp
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[CodeGen] Move instruction predicate verification to emitInstruction
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2022-07-14 09:33:28 +01:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVCodeGenPrepare.cpp
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
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2022-01-28 09:51:49 -08:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.
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2022-06-15 16:23:39 +08:00 |
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RISCVFrameLowering.cpp
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[RISCV] Add early-exit to RVV stack computation. NFCI.
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2022-07-13 08:50:08 +01:00 |
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RISCVFrameLowering.h
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[RISCV] Add early-exit to RVV stack computation. NFCI.
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2022-07-13 08:50:08 +01:00 |
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RISCVGatherScatterLowering.cpp
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[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
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2022-06-10 13:00:20 -07:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel.
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2022-07-14 18:24:10 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Remove doPeepholeLoadStoreADDI.
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2022-07-11 10:44:33 -07:00 |
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RISCVISelLowering.cpp
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[RISCV] Fold (sra (sext_inreg (shl X, C1), i32), C2) -> (sra (shl X, C1+32), C2+32).
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2022-07-13 14:34:17 -07:00 |
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RISCVISelLowering.h
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[RISCV] Exploit fact that vscale is always power of two to replace urem sequence
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2022-07-13 10:54:47 -07:00 |
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RISCVInsertVSETVLI.cpp
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Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
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2022-06-29 10:27:02 -07:00 |
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RISCVInstrFormats.td
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[RISCV] Support mask policy for RVV IR intrinsics.
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2022-03-22 01:19:16 -07:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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[RISCV] Remove Zvamo Extention
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2021-12-20 10:28:39 +08:00 |
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RISCVInstrInfo.cpp
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[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
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2022-07-03 20:18:13 +08:00 |
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RISCVInstrInfo.h
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[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
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2022-07-03 20:18:13 +08:00 |
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RISCVInstrInfo.td
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[RISCV] Add ADDI instr for computing FrameIndex address
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2022-07-04 22:13:35 +08:00 |
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RISCVInstrInfoA.td
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[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
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2022-06-03 09:00:17 -07:00 |
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RISCVInstrInfoC.td
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RISCVInstrInfoD.td
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[RISCV] Add more patterns for FNMADD
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2022-06-04 12:31:45 +08:00 |
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RISCVInstrInfoF.td
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[RISCV] Add more patterns for FNMADD
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2022-06-04 12:31:45 +08:00 |
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RISCVInstrInfoM.td
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[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
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2022-04-25 10:53:41 -07:00 |
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RISCVInstrInfoV.td
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[RISCV] Add scheduling resources for vector segment instructions.
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2022-07-12 22:51:58 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Remove true_mask patterns for VRGATHERE16..
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2022-06-21 11:59:37 -07:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Increase complexity of RVV element extraction patterns
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2022-07-11 10:53:15 +08:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Mark fminnum_vl and fmaxnum_vl as commutable.
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2022-07-08 10:19:09 -07:00 |
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RISCVInstrInfoZb.td
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[RISCV] Move some SHXADD matching cases into a ComplexPattern. NFC
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2022-07-03 21:57:05 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Add more patterns for FNMADD
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2022-06-04 12:31:45 +08:00 |
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RISCVInstrInfoZicbo.td
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[RISCV] Implement support for the Zicbop extension
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2022-06-28 12:43:26 +01:00 |
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RISCVInstrInfoZk.td
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[RISCV] Adjust some comments.
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2022-02-01 22:53:54 +08:00 |
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RISCVInstructionSelector.cpp
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[Target] Remove redundant member initialization (NFC)
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2022-01-06 22:01:44 -08:00 |
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
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2022-06-12 10:47:21 -07:00 |
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RISCVMachineFunctionInfo.cpp
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llvm-reduce: Add cloning of target MachineFunctionInfo
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2022-06-07 10:14:48 -04:00 |
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RISCVMachineFunctionInfo.h
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llvm-reduce: Add cloning of target MachineFunctionInfo
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2022-06-07 10:14:48 -04:00 |
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RISCVMacroFusion.cpp
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[RISCV] Add macrofusion infrastructure and one example usage.
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2022-06-23 08:38:39 -07:00 |
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RISCVMacroFusion.h
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[RISCV] Add macrofusion infrastructure and one example usage.
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2022-06-23 08:38:39 -07:00 |
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RISCVMakeCompressible.cpp
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[RISCV] Fix wrong register rename for store value during make-compressible optimization
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2022-07-08 18:07:17 +08:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global.
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2022-06-28 11:46:24 -07:00 |
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RISCVRedundantCopyElimination.cpp
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[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
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2022-02-04 10:43:46 -08:00 |
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RISCVRegisterBankInfo.cpp
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[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
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2022-03-27 22:22:37 -07:00 |
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RISCVRegisterBankInfo.h
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[nfc][codegen] Move RegisterBank[Info].h under CodeGen
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2022-03-01 21:53:25 -08:00 |
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
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2022-07-03 20:18:13 +08:00 |
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RISCVRegisterInfo.h
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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RISCVRegisterInfo.td
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[RISCV] Add llvm.read.register support for vlenb
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2022-05-13 09:12:02 -07:00 |
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RISCVSExtWRemoval.cpp
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[RISCV] transform MI to W variant to remove sext.w
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2022-04-22 10:59:26 -07:00 |
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RISCVSchedRocket.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVSchedSiFive7.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVSchedule.td
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RISCVScheduleB.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVScheduleV.td
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[RISCV] Add scheduling resources for vector segment instructions.
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2022-07-12 22:51:58 -07:00 |
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RISCVSubtarget.cpp
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[RISCV] Disable subregister liveness by default
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2022-07-14 17:04:10 +01:00 |
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RISCVSubtarget.h
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[RISCV] Rename getMin/MaxVLen to getArchMin/MaxVlen and make protected [nfc]
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2022-06-28 15:54:40 -07:00 |
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RISCVSystemOperands.td
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[RISCV] Initially support the K-extension instructions on the LLVM MC layer
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2022-01-24 14:45:35 +08:00 |
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RISCVTargetMachine.cpp
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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RISCVTargetMachine.h
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[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
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2022-04-08 11:55:48 +08:00 |
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Fix mistake in RISCVTTIImpl::getIntImmCostInst.
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2022-07-14 16:42:35 -07:00 |
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RISCVTargetTransformInfo.h
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[LoopVectorize] Add option to use active lane mask for loop control flow
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2022-07-11 13:46:55 +01:00 |
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