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llvm-project/llvm/test/CodeGen/MIR
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Matt Arsenault 97ed2fbc5f MIR: Fix parse error on empty CustomRegMask 2022-06-27 08:50:35 -04:00
..
AArch64 llvm-reduce: Don't assert on functions which don't track liveness 2022-06-07 10:00:25 -04:00
AMDGPU MIR: Fix parse error on empty CustomRegMask 2022-06-27 08:50:35 -04:00
ARM CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Generic [IR] Enable opaque pointers by default 2022-06-02 09:40:56 +02:00
Hexagon CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Mips CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
NVPTX
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PowerPC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
RISCV [RISCV][NFC] Add missing lit.local.cfg in test/CodeGen/MIR/RISCV/ 2022-04-08 12:10:20 +08:00
WebAssembly
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X86 Reland "Reland "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86 following the psABI"""" 2022-06-17 21:34:05 +08:00
README
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README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.