e82e4fa7ef
Add the instructions and patterns for loads and stores in microMIPSr3 when a 64 bit FPU is present. Previously, this would lead to an instruction selection failure. This resolves PR/49200. Thanks to jdeguire for reporting the issue! Differential Revision: https://reviews.llvm.org/D124723 |
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| .. | ||
| abs.ll | ||
| add-dsp.ll | ||
| add.ll | ||
| addrspacecast.ll | ||
| and.ll | ||
| arith-fp.ll | ||
| ashr.ll | ||
| atomicrmx.ll | ||
| bitcast.ll | ||
| call.ll | ||
| cvt.ll | ||
| extractelement.ll | ||
| fptosi.ll | ||
| indirectbr.ll | ||
| isel.ll | ||
| lh_lhu.ll | ||
| load-atomic.ll | ||
| load.ll | ||
| lshr.ll | ||
| mul.ll | ||
| nan-fp-attr.ll | ||
| not.ll | ||
| or.ll | ||
| ret.ll | ||
| sdiv.ll | ||
| select-dbl.ll | ||
| select-flt.ll | ||
| select-int.ll | ||
| shl.ll | ||
| sqrt.ll | ||
| srem.ll | ||
| store-atomic.ll | ||
| store.ll | ||
| sub.ll | ||
| trap.ll | ||
| udiv.ll | ||
| urem.ll | ||
| xor.ll | ||