| .. |
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GlobalISel
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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intrinsics
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…
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rvv
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[RISCV] Disable subregister liveness by default
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2022-07-14 17:04:10 +01:00 |
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MachineSink-implicit-x0.mir
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Fix minor deficiency in machine-sink.
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2021-11-12 08:01:13 +01:00 |
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O0-pipeline.ll
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[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly
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2022-05-30 17:22:50 -07:00 |
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O3-pipeline.ll
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[RISCV] Add a RISCV specific CodeGenPrepare pass.
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2022-07-14 10:20:59 -07:00 |
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add-before-shl.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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add-imm.ll
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[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
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2022-06-24 08:31:52 -07:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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[test][DAGCombine] Add more tests for carry diamond. NFC
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2022-01-27 00:25:26 +01:00 |
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addimm-mulimm.ll
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[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
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2022-06-24 08:31:52 -07:00 |
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addrspacecast.ll
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…
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aext-to-sext.ll
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[RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64.
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2022-04-11 14:38:39 -07:00 |
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align-loops.ll
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[CodeGen] Add -align-loops
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2021-08-04 12:45:18 -07:00 |
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align.ll
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…
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alloca.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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alu8.ll
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[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
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2022-07-14 16:10:14 -07:00 |
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alu16.ll
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[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
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2022-07-14 16:10:14 -07:00 |
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alu32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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alu64.ll
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[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
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2022-02-16 09:22:11 -08:00 |
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analyze-branch.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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and.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
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2022-03-16 02:10:57 +00:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-flag.ll
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…
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atomic-cmpxchg.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-rmw.ll
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[SDAG] try to replace subtract-from-constant with xor
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2022-07-08 08:14:24 -04:00 |
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atomic-signext.ll
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[SDAG] try to replace subtract-from-constant with xor
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2022-07-08 08:14:24 -04:00 |
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attributes.ll
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[RISCV] Implement support for the Zicbop extension
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2022-06-28 12:43:26 +01:00 |
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bitreverse-shift.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
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2022-03-30 11:46:42 -07:00 |
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bittest.ll
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[RISCV] Override TargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd.
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2022-05-11 11:13:17 -07:00 |
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blockaddress.ll
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…
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branch-relaxation.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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branch.ll
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…
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bswap-bitreverse.ll
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[DAGCombiner] Fix bug in MatchBSwapHWordLow.
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2022-05-18 09:23:18 -07:00 |
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bswap-shift.ll
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[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
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2022-03-30 11:46:42 -07:00 |
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byval.ll
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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callee-saved-fpr32s.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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callee-saved-fpr64s.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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callee-saved-gprs.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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calling-conv-half.ll
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[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
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2022-01-29 00:01:00 +08:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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calling-conv-ilp32.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32d.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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calling-conv-lp64.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-sext-zext.ll
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…
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calling-conv-vector-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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calls.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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cmp-bool.ll
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…
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codemodel-lowering.ll
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[RISCV] Set target-abi explicitly to reduce codegen results
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2022-06-01 13:49:23 +08:00 |
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compress-float.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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compress-inline-asm.ll
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…
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compress.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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copy-frameindex.mir
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llvm-reduce: Don't assert on functions which don't track liveness
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2022-06-07 10:00:25 -04:00 |
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copysign-casts.ll
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[RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C).
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2022-06-29 09:15:09 -07:00 |
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ctlz-cttz-ctpop.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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disable-tail-calls.ll
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…
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disjoint.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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div-by-constant.ll
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[RISCV] Refine the heuristics for our custom (mul (and X, C2), C1) isel.
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2022-07-14 18:24:10 -07:00 |
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div-pow2.ll
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[RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT
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2022-01-11 15:54:35 +08:00 |
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div.ll
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[RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3).
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2022-04-08 09:04:04 -07:00 |
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double-arith-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-arith.ll
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[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
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2022-07-13 19:37:34 +01:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Select SRLI+SLLI for AND with leading ones mask
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2022-03-16 02:10:57 +00:00 |
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double-br-fcmp.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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double-calling-conv.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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double-convert-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-convert.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-fcmp-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-fcmp.ll
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[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
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2022-07-13 19:37:34 +01:00 |
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double-frem.ll
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[RISCV] Promote f16 frem with Zfh.
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2021-11-10 17:35:07 -08:00 |
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double-imm.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-intrinsics-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-intrinsics.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-isnan.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-mem.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-previous-failure.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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double-round-conv-sat.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-round-conv.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-select-fcmp.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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double-stack-spill-restore.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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dwarf-eh.ll
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…
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early-clobber-tied-def-subreg-liveness.ll
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Reland "[SplitKit] Handle early clobber + tied to def correctly"
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2022-06-16 17:13:09 +08:00 |
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early-clobber-tied-def-subreg-liveness.mir
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Reland "[SplitKit] Handle early clobber + tied to def correctly"
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2022-06-16 17:13:09 +08:00 |
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eh-dwarf-cfa.ll
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[RISCV] Add ISD::EH_DWARF_CFA
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2022-06-08 22:03:30 +08:00 |
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elf-preemption.ll
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…
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exception-pointer-register.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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fastcc-float.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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fastcc-int.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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fixed-vectors-vadd-vp-mask.ll
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[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
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2022-04-26 02:30:22 +00:00 |
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fixed-vectors-vmul-vp-mask.ll
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[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
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2022-04-26 02:30:22 +00:00 |
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fixed-vectors-vsub-vp-mask.ll
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[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
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2022-04-26 02:30:22 +00:00 |
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fixups-diff.ll
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test: clean up some of the RISCV tests (NFC)
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2021-06-17 09:51:09 -07:00 |
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fixups-relax-diff.ll
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test: clean up some of the RISCV tests (NFC)
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2021-06-17 09:51:09 -07:00 |
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float-arith-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-arith.ll
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[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
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2022-07-13 19:37:34 +01:00 |
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float-bit-preserving-dagcombines.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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float-bitmanip-dagcombines.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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float-br-fcmp.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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float-convert-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-convert.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-fcmp-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-fcmp.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-frem.ll
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[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
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float-imm.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-intrinsics-strict.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-intrinsics.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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float-isnan.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-mem.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-round-conv-sat.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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float-round-conv.ll
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[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
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2022-01-11 09:05:57 -08:00 |
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float-select-fcmp.ll
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[RISCV] Use check-prefixes to reduce check lines
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2022-06-06 15:59:15 +08:00 |
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flt-rounds.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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fmax-fmin.ll
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[SDAG] avoid libcalls to fmin/fmax for soft-float targets
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2022-03-30 11:22:03 -04:00 |
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fold-addi-loadstore.ll
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[RISCV] Support LUI+ADDIW in doPeepholeLoadStoreADDI.
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2022-06-03 18:06:56 -07:00 |
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fold-vector-cmp.ll
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[SelectionDAG] Use correct boolean representation in FoldConstantArithmetic
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2022-04-28 18:42:16 +02:00 |
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fp-imm.ll
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[RISCV] Optimize lowering of floating-point -0.0
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2022-01-20 11:46:28 +00:00 |
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fp16-promote.ll
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[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
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2022-01-29 00:01:00 +08:00 |
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fp128.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
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fpclamptosat.ll
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[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
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fpclamptosat_vec.ll
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[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
fpenv.ll
|
…
|
|
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frame-info.ll
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[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
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frame.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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frameaddr-returnaddr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
frm-dependency.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
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get-register-invalid.ll
|
…
|
|
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get-register-noreserve.ll
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[RISCV] Add llvm.read.register support for vlenb
|
2022-05-13 09:12:02 -07:00 |
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get-register-reserve.ll
|
…
|
|
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get-setcc-result-type.ll
|
…
|
|
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ghccc-rv32.ll
|
…
|
|
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ghccc-rv64.ll
|
…
|
|
|
half-arith-strict.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-arith.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
half-bitmanip-dagcombines.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-br-fcmp.ll
|
[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
|
half-convert-strict.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-convert.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-fcmp-strict.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-fcmp.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
half-frem.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
half-imm.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-intrinsics.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-isnan.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-mem.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-round-conv-sat.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-round-conv.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
half-select-fcmp.ll
|
[RISCV] Use check-prefixes to reduce check lines
|
2022-06-06 15:59:15 +08:00 |
|
hoist-global-addr-base.ll
|
[RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global.
|
2022-06-28 11:46:24 -07:00 |
|
i32-icmp.ll
|
[RISCV][NFC] Add immediate tests for the icmp instruction
|
2022-03-30 02:51:26 +00:00 |
|
i64-icmp.ll
|
[RISCV] [NFC] Add Immediate tests for the cmov instruction
|
2022-04-06 03:08:55 +00:00 |
|
iabs.ll
|
[LegalizeTypes][RISCV][WebAssembly] Expand ABS in PromoteIntRes_ABS if it will expand to sra+xor+sub later.
|
2022-03-15 08:27:39 -07:00 |
|
imm-cse.ll
|
…
|
|
|
imm.ll
|
[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.
|
2022-04-29 08:58:32 -07:00 |
|
indirectbr.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
init-array.ll
|
…
|
|
|
inline-asm-S-constraint.ll
|
[RISCV] Support machine constraint "S"
|
2021-07-13 09:30:09 -07:00 |
|
inline-asm-abi-names.ll
|
…
|
|
|
inline-asm-clobbers.ll
|
[RISCV] Update computeTargetABI from llc as well as clang
|
2022-02-24 21:55:44 -08:00 |
|
inline-asm-d-abi-names.ll
|
…
|
|
|
inline-asm-d-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm-f-abi-names.ll
|
…
|
|
|
inline-asm-f-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm-i-constraint-i1.ll
|
…
|
|
|
inline-asm-invalid.ll
|
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
|
2021-12-23 20:32:36 -06:00 |
|
inline-asm-zfh-constraint-f.ll
|
[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.
|
2022-03-02 11:22:46 -08:00 |
|
inline-asm.ll
|
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
|
2022-01-06 08:13:42 -08:00 |
|
interrupt-attr-args-error.ll
|
…
|
|
|
interrupt-attr-callee.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-invalid.ll
|
…
|
|
|
interrupt-attr-nocall.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-ret-error.ll
|
…
|
|
|
interrupt-attr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
isel-optnone.ll
|
[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly
|
2022-05-30 17:22:50 -07:00 |
|
jumptable.ll
|
[RISCV] Generate 32 bits jumptable entries when code model is small
|
2022-01-11 18:20:37 +08:00 |
|
large-stack.ll
|
[RISCV] Merge addi into load/store as there is a ADD between them
|
2022-04-29 04:33:05 +00:00 |
|
legalize-fneg.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
lit.local.cfg
|
…
|
|
|
live-sp.mir
|
[RISCV] Fix invalid kill on callee save
|
2021-11-02 11:56:54 +00:00 |
|
loop-strength-reduce-add-cheaper-than-mul.ll
|
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
|
2022-05-27 11:05:18 -07:00 |
|
loop-strength-reduce-loop-invar.ll
|
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
|
2022-05-27 11:05:18 -07:00 |
|
lsr-legaladdimm.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
machine-cp.mir
|
[MachineCopyPropagation][RISCV] Fix D125335 accidentally change control flow.
|
2022-06-17 21:40:08 -07:00 |
|
machine-cse.ll
|
[RISCV] Add isCommutable to FADD/FMUL/FMIN/FMAX/FEQ.
|
2022-05-02 20:21:16 -07:00 |
|
machine-outliner-cfi.mir
|
[RISCV] Precommit test for D122634
|
2022-04-22 12:19:55 +08:00 |
|
machine-outliner-patchable.ll
|
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
|
2021-12-13 13:24:29 -08:00 |
|
machine-outliner-position.mir
|
[RISCV] Precommit test for D122634
|
2022-04-22 12:19:55 +08:00 |
|
machine-outliner-throw.ll
|
[RISCV] Do not outline CFI instructions when they are needed in EH
|
2022-04-22 12:28:19 +08:00 |
|
machinelicm-address-pseudos.ll
|
[RISCV] Ensure PseudoLA* can be hoisted
|
2022-03-16 18:45:36 +00:00 |
|
machineoutliner-jumptable.mir
|
[RISCV] Fix Machine Outliner jump table handling.
|
2021-09-09 07:32:30 +02:00 |
|
machineoutliner.mir
|
…
|
|
|
macro-fusion-lui-addi.ll
|
[RISCV] Add macrofusion infrastructure and one example usage.
|
2022-06-23 08:38:39 -07:00 |
|
make-compressible-for-store-address.mir
|
[RISCV] Fix wrong register rename for store value during make-compressible optimization
|
2022-07-08 18:07:17 +08:00 |
|
make-compressible-rv64.mir
|
[RISCV] Add pre-emit pass to make more instructions compressible
|
2022-05-25 09:25:02 +01:00 |
|
make-compressible.mir
|
[RISCV] Add pre-emit pass to make more instructions compressible
|
2022-05-25 09:25:02 +01:00 |
|
mattr-invalid-combination.ll
|
[RISCV] Remove check and update test file in D121183
|
2022-03-24 00:48:52 +08:00 |
|
mem.ll
|
[RISCV] Add tests for (load (add X, [2048,4094])). NFC
|
2022-06-27 13:42:57 -07:00 |
|
mem64.ll
|
[RISCV] Make custom isel for (add X, imm) used by load/stores more selective.
|
2022-06-30 14:20:11 -07:00 |
|
memcpy-inline.ll
|
[RISCV] Teach shouldConvertConstantLoadToIntImm that constant materialization can use constant pools.
|
2022-07-10 14:10:17 -07:00 |
|
min-max.ll
|
[SelectionDAG] Further improve computeKnownBits for (smax X, C) where C is non-negative.
|
2022-06-06 09:59:23 -07:00 |
|
mir-target-flags.ll
|
[RISCV] Ensure PseudoLA* can be hoisted
|
2022-03-16 18:45:36 +00:00 |
|
miss-sp-restore-eh.ll
|
[RISCV] Fix missing stack pointer recover
|
2022-06-09 23:38:50 +08:00 |
|
module-target-abi.ll
|
…
|
|
|
module-target-abi2.ll
|
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
|
2022-03-24 00:48:52 +08:00 |
|
mul.ll
|
[SelectionDAG] fold 'Op0 - (X * MulC)' to 'Op0 + (X << log2(-MulC))'
|
2022-06-15 05:50:18 +00:00 |
|
musttail-call.ll
|
…
|
|
|
neg-abs.ll
|
[DAGCombiner] Don't expand (neg (abs x)) if the abs has an additional user.
|
2022-03-01 07:32:07 -08:00 |
|
nomerge.ll
|
…
|
|
|
option-nopic.ll
|
…
|
|
|
option-norelax.ll
|
…
|
|
|
option-norvc.ll
|
…
|
|
|
option-pic.ll
|
…
|
|
|
option-relax.ll
|
…
|
|
|
option-rvc.ll
|
…
|
|
|
optnone-store-no-combine.ll
|
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
|
2021-12-23 10:48:28 +05:30 |
|
out-of-reach-emergency-slot.mir
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
overflow-intrinsic-optimizations.ll
|
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
|
2021-08-31 11:23:56 -07:00 |
|
patchable-function-entry.ll
|
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
|
2021-05-29 15:11:37 +01:00 |
|
pic-models.ll
|
…
|
|
|
pr40333.ll
|
…
|
|
|
pr51206.ll
|
[RISCV] Use MULHU for more division by constant cases.
|
2021-12-09 09:10:14 -08:00 |
|
pr53662.mir
|
[RISCV] Don't getDebugLoc for the end node of MBB iterator
|
2022-04-30 16:00:20 +08:00 |
|
pr55201.ll
|
[DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.
|
2022-04-30 11:02:30 -07:00 |
|
pr56110.ll
|
[DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore.
|
2022-06-19 15:50:15 -07:00 |
|
pr56457.ll
|
[TargetLowering][RISCV] Make expandCTLZ work for non-power of 2 types.
|
2022-07-12 11:36:37 -07:00 |
|
prefetch.ll
|
…
|
|
|
readcyclecounter.ll
|
…
|
|
|
regalloc-last-chance-recoloring-failure.ll
|
Revert "[RISCV] Enable subregister liveness tracking for RVV."
|
2022-05-13 10:59:58 -07:00 |
|
rem.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
remat.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
reserved-reg-errors.ll
|
…
|
|
|
reserved-regs.ll
|
…
|
|
|
riscv-codegenprepare-asm.ll
|
[RISCV] Add a RISCV specific CodeGenPrepare pass.
|
2022-07-14 10:20:59 -07:00 |
|
riscv-codegenprepare.ll
|
[RISCV] Add a RISCV specific CodeGenPrepare pass.
|
2022-07-14 10:20:59 -07:00 |
|
rotl-rotr.ll
|
[LegalizeTypes] Fix bug in expensive checks verification
|
2022-05-26 13:13:32 -07:00 |
|
rv32e.ll
|
…
|
|
|
rv32i-rv64i-float-double.ll
|
[NFC][llvm] Inclusive language: reword uses of sanity test and check
|
2021-11-25 07:21:42 -05:00 |
|
rv32i-rv64i-half.ll
|
[RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
|
2022-01-29 00:01:00 +08:00 |
|
rv32zba.ll
|
[RISCV][NFC] Simplify tests by reorganizing check prefixes
|
2022-05-12 02:22:56 +00:00 |
|
rv32zbb-intrinsic.ll
|
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
|
2022-03-28 16:56:33 -07:00 |
|
rv32zbb-zbp-zbkb.ll
|
[RISCV][NFC] Simplify tests by reorganizing check prefixes
|
2022-05-12 02:22:56 +00:00 |
|
rv32zbb.ll
|
[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
|
rv32zbc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbc-zbkc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbe-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbf-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbkb-intrinsic.ll
|
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
|
2022-01-30 12:41:09 -08:00 |
|
rv32zbkx-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbp-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv32zbp-zbkb.ll
|
[RISCV][NFC] Simplify tests by reorganizing check prefixes
|
2022-05-12 02:22:56 +00:00 |
|
rv32zbp.ll
|
[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
|
2022-05-14 09:50:01 +01:00 |
|
rv32zbr.ll
|
…
|
|
|
rv32zbs.ll
|
[RISCV][NFC] Simplify tests by reorganizing check prefixes
|
2022-05-12 02:22:56 +00:00 |
|
rv32zbt-intrinsic.ll
|
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
|
2022-03-05 21:26:51 -08:00 |
|
rv32zbt.ll
|
[RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3).
|
2022-04-08 09:04:04 -07:00 |
|
rv32zknd-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv32zkne-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv32zknh-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv32zksed-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv32zksh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64-large-stack.ll
|
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
|
2021-07-20 09:22:06 -07:00 |
|
rv64d-double-convert-strict.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
rv64d-double-convert.ll
|
[RISCV] Update some tests to use floating point ABI where it makes sense.
|
2022-02-24 09:27:57 -08:00 |
|
rv64f-float-convert-strict.ll
|
[RISCV] Set target-abi explicitly to reduce codegen results
|
2022-06-01 13:49:23 +08:00 |
|
rv64f-float-convert.ll
|
[RISCV] Set target-abi explicitly to reduce codegen results
|
2022-06-01 13:49:23 +08:00 |
|
rv64i-complex-float.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
rv64i-demanded-bits.ll
|
[SelectionDAG] Teach computeKnownBits that a nsw self multiply produce a positive value.
|
2022-06-08 14:55:58 -07:00 |
|
rv64i-double-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-exhaustive-w-insts.ll
|
[RISCV][NFC] Remove solved TODO for combining constant shifts
|
2022-05-26 09:55:19 +08:00 |
|
rv64i-shift-sext.ll
|
[RISCV] Fold (sra (sext_inreg (shl X, C1), i32), C2) -> (sra (shl X, C1+32), C2+32).
|
2022-07-13 14:34:17 -07:00 |
|
rv64i-single-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-tricky-shifts.ll
|
…
|
|
|
rv64i-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64m-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64zba.ll
|
[RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1)
|
2022-07-05 16:21:47 -07:00 |
|
rv64zbb-intrinsic.ll
|
[RISCV] Add computeKnownBits support for RISCVISD::GORC.
|
2022-03-28 16:56:33 -07:00 |
|
rv64zbb-zbp-zbkb.ll
|
[RISCV][NFC] Simplify tests by reorganizing check prefixes
|
2022-05-12 02:22:56 +00:00 |
|
rv64zbb.ll
|
[RISCV] Restore "Enable shrink wrap by default"
|
2022-07-02 11:13:13 +08:00 |
|
rv64zbc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbc-zbkc-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbe-intrinsic.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv64zbf-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbkb-intrinsic.ll
|
[RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV.
|
2022-01-30 12:41:09 -08:00 |
|
rv64zbkx-intrinsic.ll
|
[RISCV] Fix the indentation of 'ret' in rv*zb*-intrinsic.ll tests. NFC
|
2022-03-01 11:37:49 -08:00 |
|
rv64zbp-intrinsic.ll
|
[RISCV] Implement RISCVTargetLowering::getTargetConstantFromLoad.
|
2022-06-16 15:11:18 -07:00 |
|
rv64zbp-zbkb.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zbp.ll
|
[RISCV] Implement RISCVTargetLowering::getTargetConstantFromLoad.
|
2022-06-16 15:11:18 -07:00 |
|
rv64zbr.ll
|
…
|
|
|
rv64zbs.ll
|
[RISCV][NFC] Simplify tests by reorganizing check prefixes
|
2022-05-12 02:22:56 +00:00 |
|
rv64zbt-intrinsic.ll
|
[RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.
|
2022-03-05 21:26:51 -08:00 |
|
rv64zbt.ll
|
[RISCV] transform MI to W variant to remove sext.w
|
2022-04-22 10:59:26 -07:00 |
|
rv64zfh-half-convert-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zfh-half-convert.ll
|
[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
|
2022-02-24 09:19:01 -08:00 |
|
rv64zfh-half-intrinsics-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zfh-half-intrinsics.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
rv64zknd-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zknd-zkne-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zkne-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zknh-intrinsic.ll
|
[RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
|
2022-07-13 19:37:34 +01:00 |
|
rv64zksed-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
rv64zksh-intrinsic.ll
|
[RISCV][CodeGen] Implement IR Intrinsic support for K extension
|
2022-01-27 15:53:35 +08:00 |
|
sadd_sat.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
sadd_sat_plus.ll
|
[RISCV] Set CostPerUse to 1 iff RVC is enabled
|
2022-01-21 14:44:26 +08:00 |
|
saverestore.ll
|
…
|
|
|
scalable-vector-struct.ll
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[RISCV] Remove experimental prefix from rvv-related extensions.
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2022-01-22 20:18:40 -08:00 |
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sdata-limit-0.ll
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…
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sdata-limit-4.ll
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…
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sdata-limit-8.ll
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…
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sdata-local-sym.ll
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…
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select-and.ll
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…
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select-bare.ll
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…
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select-binop-identity.ll
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[RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y))
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2021-08-10 09:02:56 -07:00 |
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select-cc.ll
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[RISCV] Add CMOV isel pattern for (select (setgt X, Imm), Y, Z)
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2022-04-07 05:55:53 +00:00 |
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select-const.ll
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[RISCV] Update computeTargetABI from llc as well as clang
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2022-02-24 21:55:44 -08:00 |
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select-constant-xor.ll
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[RISCV] Optimize LI+SLT to SLTI+XORI for immediates in specific range
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2022-03-29 14:46:49 +08:00 |
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select-optimize-multiple.ll
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[RISCV] Optimize 2x SELECT for floating-point types
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2022-07-11 14:10:27 +08:00 |
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select-optimize-multiple.mir
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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select-or.ll
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…
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selectcc-to-shiftand.ll
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[RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C).
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2022-06-29 09:15:09 -07:00 |
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setcc-logic.ll
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[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
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2021-08-18 10:44:25 -07:00 |
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sext-zext-trunc.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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sextw-removal.ll
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[RISCV] transform MI to W variant to remove sext.w
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2022-04-22 10:59:26 -07:00 |
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shadowcallstack.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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shift-and.ll
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[RISCV] Add another isel optimization for (and (shl x, c2), c1)
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2021-09-23 14:18:07 -07:00 |
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shift-masked-shamt.ll
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[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
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2022-02-16 09:22:11 -08:00 |
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shifts.ll
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[RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.
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2022-02-16 09:22:11 -08:00 |
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shl-demanded.ll
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[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
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2022-07-14 16:10:14 -07:00 |
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shlimm-addimm.ll
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[RISCV][test] Add tests of (add (shl r, c0), c1)
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2021-10-14 14:53:03 +00:00 |
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shrinkwrap.ll
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[RISCV] Restore "Enable shrink wrap by default"
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2022-07-02 11:13:13 +08:00 |
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sink-icmp.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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spill-fpr-scalar.ll
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[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
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2022-03-17 10:04:02 -07:00 |
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split-offsets.ll
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[RISCV] Modify the custom isel for (add X, imm) used by load/stores.
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2022-07-09 22:47:27 -07:00 |
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split-sp-adjust.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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srem-lkk.ll
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[RISCV] Use constant pool for large integers
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2021-12-31 14:48:48 +08:00 |
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srem-seteq-illegal-types.ll
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[RISCV] Add ADDI instr for computing FrameIndex address
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2022-07-04 22:13:35 +08:00 |
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srem-vector-lkk.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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ssub_sat.ll
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[RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
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2022-04-13 10:01:07 +00:00 |
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ssub_sat_plus.ll
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[RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
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2022-04-13 10:01:07 +00:00 |
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stack-realignment-with-variable-sized-objects.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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stack-realignment.ll
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[RISCV] Use two ADDIs to do some stack pointer adjustments.
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2022-05-31 10:25:28 -07:00 |
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stack-slot-size.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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stack-store-check.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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subtarget-features-std-ext.ll
|
…
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switch-width.ll
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[riscv] Add a bunch of tests exploring switch lowering
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2022-05-11 13:16:31 -07:00 |
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tail-calls.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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target-abi-invalid.ll
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…
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target-abi-valid.ll
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…
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thread-pointer.ll
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…
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tls-models.ll
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…
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uadd_sat.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
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2022-01-12 19:33:44 +00:00 |
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uadd_sat_plus.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
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2022-01-12 19:33:44 +00:00 |
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umulo-128-legalisation-lowering.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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unaligned-load-store.ll
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[RISCV] Add a subtarget feature to enable unaligned scalar loads and stores
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2022-05-26 15:25:47 -07:00 |
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unfold-masked-merge-scalar-variablemask.ll
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[RISCV][NFC] Reorganize check prefixes in some tests to reduce redundant lines
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2022-04-13 10:01:07 +00:00 |
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unroll-loop-cse.ll
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Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
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2022-02-17 17:27:37 +08:00 |
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urem-lkk.ll
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[RISCV] Use constant pool for large integers
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2021-12-31 14:48:48 +08:00 |
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urem-seteq-illegal-types.ll
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[RISCV] Add ADDI instr for computing FrameIndex address
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2022-07-04 22:13:35 +08:00 |
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urem-vector-lkk.ll
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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usub_sat.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
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usub_sat_plus.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
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vadd-vp-mask.ll
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[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
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2022-04-26 02:30:22 +00:00 |
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vararg.ll
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[RISCV] Use SelectionDAG::isBaseWithConstantOffset in scalar load/store address matching.
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2022-06-03 10:55:28 -07:00 |
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vec3-setcc-crash.ll
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[DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
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2022-05-14 09:50:01 +01:00 |
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vector-abi.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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verify-instr.mir
|
…
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|
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vlenb.ll
|
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
|
2022-05-16 16:38:30 -07:00 |
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vmul-vp-mask.ll
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[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
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2022-04-26 02:30:22 +00:00 |
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vsub-vp-mask.ll
|
[RISCV][SelectionDAG] Support VP_ADD/VP_MUL/VP_SUB mask operations
|
2022-04-26 02:30:22 +00:00 |
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wide-mem.ll
|
…
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|
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xaluo.ll
|
[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
|
2022-06-24 08:31:52 -07:00 |
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zext-with-load-is-free.ll
|
[RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.
|
2022-05-27 11:05:18 -07:00 |
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zfh-half-intrinsics-strict.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
|
zfh-half-intrinsics.ll
|
[RISCV] update zfh and zfhmin extention to v1.0
|
2022-01-15 09:21:24 +08:00 |
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zfh-imm.ll
|
[RISCV] Optimize lowering of floating-point -0.0
|
2022-01-20 11:46:28 +00:00 |
79016f6eef