llvm-project/llvm/test/Transforms/CodeGenPrepare
Nikita Popov c10921fa1a [CGP] Also freeze ctlz/cttz operand when despeculating
D125887 changed the ctlz/cttz despeculation transform to insert
a freeze for the introduced branch on zero. While this does fix
the "branch on poison" issue, we may still get in trouble if we
pick a different value for the branch and for the ctz argument
(i.e. non-zero for the branch, but zero for the ctz). To avoid
this, we should use the same frozen value in both positions.

This does cause a regression in RISCV codegen by introducing an
additional sext. The DAG looks like this:

    t0: ch = EntryToken
        t2: i64,ch = CopyFromReg t0, Register:i64 %3
      t4: i64 = AssertSext t2, ValueType:ch:i32
    t23: i64 = freeze t4
          t9: ch = CopyToReg t0, Register:i64 %0, t23
          t16: ch = CopyToReg t0, Register:i64 %4, Constant:i64<32>
        t18: ch = TokenFactor t9, t16
            t25: i64 = sign_extend_inreg t23, ValueType:ch:i32
          t24: i64 = setcc t25, Constant:i64<0>, seteq:ch
        t28: i64 = and t24, Constant:i64<1>
      t19: ch = brcond t18, t28, BasicBlock:ch<cond.end 0x8311f68>
    t21: ch = br t19, BasicBlock:ch<cond.false 0x8311e80>

I don't see a really obvious way to improve this, as we can't push
the freeze past the AssertSext (which may produce poison).

Differential Revision: https://reviews.llvm.org/D126638
2022-06-10 09:46:10 +02:00
..
AArch64 [AArch64] Add support for FMA intrinsics to shouldSinkOperands. 2022-05-27 10:37:03 +01:00
AMDGPU
ARM [CodeGenPrepare] The instruction to be sunk should be inserted before its user in a block 2021-08-17 18:58:15 +08:00
Mips
NVPTX
PowerPC
RISCV [CodeGenPrepare] Avoid a scalable-vector crash in ctlz/cttz 2021-10-20 16:45:55 +01:00
SPARC
X86 [CGP] Also freeze ctlz/cttz operand when despeculating 2022-06-10 09:46:10 +02:00
dom-tree.ll [test] Test domtree validity with -verify-dom-info instead of -analyze 2022-02-09 16:00:18 -08:00
sink-shift-and-trunc.ll
skip-merging-case-block.ll