llvm-project/llvm/test/tools/llvm-mca/X86/Barcelona
Craig Topper 56d6ccd4cb [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs
Most Intel CPU scheduler files lumped the immediate and 1 instructions
together, but uops.info shows they are quite different.

For the most part the by 1 instructions were pretty accurate to the uops.info
data except the latency was 3 instead of 2 as uops.info indicates.

The by immediate instructions need 7 or 8 uops and have higher latency.

It looks like the 8-bit by immediate instructions may need even more
uops, but I just lumped them with the 16/32/64.

Noticed while checking out PR53648. So mostly I cared about the by 1
instructions.

Reviewed By: RKSimon, pengfei

Differential Revision: https://reviews.llvm.org/D119217
2022-02-08 09:20:20 -08:00
..
clear-super-register-1.s
clear-super-register-2.s
dependency-breaking-cmp.s
dependency-breaking-pcmpeq.s
dependency-breaking-pcmpgt.s
dependency-breaking-sbb-1.s
dependency-breaking-sbb-2.s
int-to-fpu-forwarding-1.s
int-to-fpu-forwarding-2.s
int-to-fpu-forwarding-3.s
load-store-throughput.s
load-throughput.s
one-idioms.s
partial-reg-update-2.s
partial-reg-update-3.s
partial-reg-update-4.s
partial-reg-update-5.s
partial-reg-update-6.s
partial-reg-update-7.s
partial-reg-update.s
rcu-statistics.s
read-advance-1.s
read-advance-2.s
read-advance-3.s
reg-move-elimination-1.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00
reg-move-elimination-2.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00
reg-move-elimination-3.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00
reg-move-elimination-4.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00
reg-move-elimination-5.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00
reg-move-elimination-6.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00
resources-3dnow.s
resources-cmov.s
resources-cmpxchg.s
resources-lea.s
resources-lzcnt.s
resources-mmx.s
resources-popcnt.s
resources-prefetchw.s
resources-sse1.s
resources-sse2.s
resources-sse3.s
resources-sse4a.s
resources-x86_32.s
resources-x86_64.s [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs 2022-02-08 09:20:20 -08:00
resources-x87.s
store-throughput.s
zero-idioms.s [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models 2022-01-19 11:29:33 +00:00