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expand_single_elem_build_vec.ll
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extract_elt.ll
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fastcc_callee.ll
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fastcc_caller.ll
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feature_vpu.ll
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insert_elt.ll
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vec_add.ll
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vec_and.ll
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vec_broadcast.ll
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vec_fcmp.ll
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[VE] v256.32|64 setcc isel and tests
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2022-02-08 13:20:55 +01:00 |
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vec_icmp.ll
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[VE] v256.32|64 setcc isel and tests
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2022-02-08 13:20:55 +01:00 |
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vec_select.ll
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[VE] select|vp.merge|vp.select v256 isel and tests
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2022-01-17 15:58:54 +01:00 |
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vp_add.ll
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vp_and.ll
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vp_ashr.ll
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[VE] SHL,SRA,SRL v256i32|64 isel and tests
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2021-12-15 11:32:18 +01:00 |
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vp_fadd.ll
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[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
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2021-12-21 09:15:31 +01:00 |
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vp_fadd_merge.ll
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[VE] vp_select+vectorBinOp passthru isel and tests
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2022-01-18 11:31:14 +01:00 |
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vp_fdiv.ll
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[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
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2021-12-21 09:15:31 +01:00 |
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vp_fdiv_merge.ll
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[VE] vp_select+vectorBinOp passthru isel and tests
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2022-01-18 11:31:14 +01:00 |
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vp_fmul.ll
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[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
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2021-12-21 09:15:31 +01:00 |
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vp_fmul_merge.ll
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[VE] vp_select+vectorBinOp passthru isel and tests
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2022-01-18 11:31:14 +01:00 |
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vp_fsub.ll
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[VE] FADD,FSUB,FMUL,FDIV v256f32|f64 isel and tests
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2021-12-21 09:15:31 +01:00 |
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vp_fsub_merge.ll
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[VE] vp_select+vectorBinOp passthru isel and tests
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2022-01-18 11:31:14 +01:00 |
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vp_lshr.ll
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[VE] SHL,SRA,SRL v256i32|64 isel and tests
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2021-12-15 11:32:18 +01:00 |
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vp_merge.ll
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[VE] select|vp.merge|vp.select v256 isel and tests
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2022-01-17 15:58:54 +01:00 |
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vp_mul.ll
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vp_or.ll
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vp_sdiv.ll
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[VE] U|SDIV v256i32|64 isel and tests
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2021-12-21 08:51:01 +01:00 |
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vp_select.ll
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[VE] select|vp.merge|vp.select v256 isel and tests
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2022-01-17 15:58:54 +01:00 |
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vp_shl.ll
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[VE] SHL,SRA,SRL v256i32|64 isel and tests
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2021-12-15 11:32:18 +01:00 |
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vp_sra.ll
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[VE] SHL,SRA,SRL v256i32|64 isel and tests
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2021-12-15 11:32:18 +01:00 |
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vp_srem.ll
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vp_srl.ll
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[VE] SHL,SRA,SRL v256i32|64 isel and tests
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2021-12-15 11:32:18 +01:00 |
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vp_sub.ll
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vp_udiv.ll
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[VE] U|SDIV v256i32|64 isel and tests
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2021-12-21 08:51:01 +01:00 |
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vp_urem.ll
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vp_xor.ll
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