llvm-project/llvm/test/MC/Disassembler
Zoran Jovanovic 85a53a1ed5 [mips][microMIPSr6] Implement SEB and SEH instructions
Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
2015-05-27 15:39:47 +00:00
..
AArch64 AArch64: add BFC alias for the BFI/BFM instructions. 2015-04-30 18:28:58 +00:00
ARM [ARM] Add v8.1a "Privileged Access Never" extension 2015-04-16 11:34:25 +00:00
Hexagon [Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests. 2015-02-03 19:15:11 +00:00
Mips [mips][microMIPSr6] Implement SEB and SEH instructions 2015-05-27 15:39:47 +00:00
PowerPC This patch adds support for the vector quadword add/sub instructions introduced 2015-05-25 15:49:26 +00:00
Sparc Sparc: Support PSR, TBR, WIM read/write instructions. 2015-05-18 16:38:47 +00:00
SystemZ [SystemZ] Add z13 vector facility and MC support 2015-05-05 19:23:40 +00:00
X86 [X86] Fix PR23271 - RIP-relative decoding bug in disassembler. 2015-05-13 22:44:52 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00