141 lines
4.0 KiB
YAML
141 lines
4.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: reg_sequence_ss_vreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: reg_sequence_ss_vreg
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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...
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---
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name: reg_sequence_ss_physreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: reg_sequence_ss_physreg
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1
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%0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1
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...
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---
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name: reg_sequence_sv_vreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: reg_sequence_sv_vreg
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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...
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---
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name: reg_sequence_sv_physreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: reg_sequence_sv_physreg
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
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%0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
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...
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---
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name: reg_sequence_vs_vreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: reg_sequence_vs_vreg
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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...
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---
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name: reg_sequence_vs_physreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: reg_sequence_vs_physreg
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1
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%0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1
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...
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---
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name: reg_sequence_vv_vreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: reg_sequence_vv_vreg
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
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...
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---
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name: reg_sequence_vv_physreg
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: reg_sequence_vv_physreg
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1
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%0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1
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...
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