271 lines
11 KiB
LLVM
271 lines
11 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-NOSDWA -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-SDWA -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
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declare i7 @llvm.cttz.i7(i7, i1) nounwind readnone
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declare i8 @llvm.cttz.i8(i8, i1) nounwind readnone
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declare i16 @llvm.cttz.i16(i16, i1) nounwind readnone
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
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declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; FUNC-LABEL: {{^}}s_cttz_zero_undef_i32:
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; SI: s_load_dword [[VAL:s[0-9]+]],
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; SI: s_ff1_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_i32:
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; SI: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]],
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; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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%val = load i32, i32 addrspace(1)* %in.gep, align 4
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_v2i32:
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; SI: {{buffer|flat}}_load_dwordx2
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: buffer_store_dwordx2
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid
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%val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8
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%cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
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store <2 x i32> %cttz, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_v4i32:
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; SI: {{buffer|flat}}_load_dwordx4
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: buffer_store_dwordx4
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @v_cttz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid
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%val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16
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%cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
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store <4 x i32> %cttz, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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; FUNC-LABEL: {{^}}s_cttz_zero_undef_i8_with_select:
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; SI: s_ff1_i32_b32 s{{[0-9]+}}, s{{[0-9]+}}
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; EG: MEM_RAT MSKOR
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; EG: FFBL_INT
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define amdgpu_kernel void @s_cttz_zero_undef_i8_with_select(i8 addrspace(1)* noalias %out, i8 %val) nounwind {
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%cttz = tail call i8 @llvm.cttz.i8(i8 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i8 %val, 0
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%ret = select i1 %cttz_ret, i8 %cttz, i8 32
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store i8 %cttz, i8 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_cttz_zero_undef_i16_with_select:
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; SI: s_ff1_i32_b32 s{{[0-9]+}}, s{{[0-9]+}}
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; EG: MEM_RAT MSKOR
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; EG: FFBL_INT
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define amdgpu_kernel void @s_cttz_zero_undef_i16_with_select(i16 addrspace(1)* noalias %out, i16 %val) nounwind {
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%cttz = tail call i16 @llvm.cttz.i16(i16 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i16 %val, 0
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%ret = select i1 %cttz_ret, i16 %cttz, i16 32
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store i16 %cttz, i16 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_cttz_zero_undef_i32_with_select:
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; SI: s_ff1_i32_b32
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define amdgpu_kernel void @s_cttz_zero_undef_i32_with_select(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%cttz = tail call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i32 %val, 0
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%ret = select i1 %cttz_ret, i32 %cttz, i32 32
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_cttz_zero_undef_i64_with_select:
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; SI: s_ff1_i32_b32 s{{[0-9]+}}, s{{[0-9]+}}
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; SI: s_ff1_i32_b32 s{{[0-9]+}}, s{{[0-9]+}}
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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define amdgpu_kernel void @s_cttz_zero_undef_i64_with_select(i64 addrspace(1)* noalias %out, i64 %val) nounwind {
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%cttz = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i64 %val, 0
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%ret = select i1 %cttz_ret, i64 %cttz, i64 32
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store i64 %cttz, i64 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_i8_with_select:
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; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI-SDWA: v_ffbl_b32_sdwa
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; EG: MEM_RAT MSKOR
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define amdgpu_kernel void @v_cttz_zero_undef_i8_with_select(i8 addrspace(1)* noalias %out, i8 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i8, i8 addrspace(1)* %arrayidx, align 1
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%cttz = tail call i8 @llvm.cttz.i8(i8 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i8 %val, 0
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%ret = select i1 %cttz_ret, i8 %cttz, i8 32
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store i8 %ret, i8 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_i16_with_select:
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; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI-SDWA: v_ffbl_b32_sdwa
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; EG: MEM_RAT MSKOR
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define amdgpu_kernel void @v_cttz_zero_undef_i16_with_select(i16 addrspace(1)* noalias %out, i16 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i16, i16 addrspace(1)* %arrayidx, align 1
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%cttz = tail call i16 @llvm.cttz.i16(i16 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i16 %val, 0
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%ret = select i1 %cttz_ret, i16 %cttz, i16 32
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store i16 %ret, i16 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_i32_with_select:
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; SI: v_ffbl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_cmp_ne_u32_e32 vcc, 0
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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define amdgpu_kernel void @v_cttz_zero_undef_i32_with_select(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i32, i32 addrspace(1)* %arrayidx, align 1
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%cttz = tail call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i32 %val, 0
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%ret = select i1 %cttz_ret, i32 %cttz, i32 32
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store i32 %ret, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_i64_with_select:
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; SI-NOSDWA: v_or_b32_e32
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; SI-NOSDWA: v_or_b32_e32
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; SI-NOSDWA: v_or_b32_e32
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; SI-SDWA: v_or_b32_sdwa
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; SI-NOSDWA: v_or_b32_e32
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; SI-SDWA: v_or_b32_sdwa
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; SI: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
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; SI-DAG: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
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; SI-DAG: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL2]]
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; SI: v_cmp_eq_u32_e32 vcc, 0
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; SI: v_cmp_ne_u64_e32 vcc, 0
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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define amdgpu_kernel void @v_cttz_zero_undef_i64_with_select(i64 addrspace(1)* noalias %out, i64 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i64, i64 addrspace(1)* %arrayidx, align 1
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%cttz = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) nounwind readnone
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%cttz_ret = icmp ne i64 %val, 0
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%ret = select i1 %cttz_ret, i64 %cttz, i64 32
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store i64 %ret, i64 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_i32_sel_eq_neg1:
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; SI: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL:v[0-9]+]]
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; SI: v_cmp_ne_u32_e32 vcc, 0, [[VAL]]
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; EG: FFBL_INT
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define amdgpu_kernel void @v_cttz_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i32, i32 addrspace(1)* %arrayidx, align 1
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%ctlz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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%cmp = icmp eq i32 %val, 0
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%sel = select i1 %cmp, i32 -1, i32 %ctlz
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store i32 %sel, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_i32_sel_ne_neg1:
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; SI: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL:v[0-9]+]]
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; SI: v_cmp_ne_u32_e32 vcc, 0, [[VAL]]
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; EG: FFBL_INT
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define amdgpu_kernel void @v_cttz_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i32, i32 addrspace(1)* %arrayidx, align 1
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%ctlz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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%cmp = icmp ne i32 %val, 0
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%sel = select i1 %cmp, i32 %ctlz, i32 -1
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store i32 %sel, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_i32_sel_ne_bitwidth:
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; SI: v_ffbl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_cmp
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; SI: v_cndmask
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW
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; EG: FFBL_INT
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define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(i32 addrspace(1)* noalias %out, i32 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i32, i32 addrspace(1)* %arrayidx, align 1
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%ctlz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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%cmp = icmp ne i32 %ctlz, 32
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%sel = select i1 %cmp, i32 %ctlz, i32 -1
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store i32 %sel, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_i8_sel_eq_neg1:
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; SI: {{buffer|flat}}_load_ubyte
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; SI-NOSDWA: v_ffbl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI-SDWA: v_ffbl_b32_sdwa
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; EG: MEM_RAT MSKOR
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; EG: FFBL_INT
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define amdgpu_kernel void @v_cttz_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i8, i8 addrspace(1)* %arrayidx, align 1
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%ctlz = call i8 @llvm.cttz.i8(i8 %val, i1 false) nounwind readnone
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%cmp = icmp eq i8 %val, 0
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%sel = select i1 %cmp, i8 -1, i8 %ctlz
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store i8 %sel, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_i16_sel_eq_neg1:
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; SI: {{buffer|flat}}_load_ubyte
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; SI: v_ffbl_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}
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; SI: buffer_store_short
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; EG: MEM_RAT MSKOR
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; EG: FFBL_INT
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define amdgpu_kernel void @v_cttz_i16_sel_eq_neg1(i16 addrspace(1)* noalias %out, i16 addrspace(1)* nocapture readonly %arrayidx) nounwind {
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%val = load i16, i16 addrspace(1)* %arrayidx, align 1
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%ctlz = call i16 @llvm.cttz.i16(i16 %val, i1 false) nounwind readnone
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%cmp = icmp eq i16 %val, 0
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%sel = select i1 %cmp, i16 -1, i16 %ctlz
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store i16 %sel, i16 addrspace(1)* %out
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ret void
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}
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