llvm-project/llvm/lib/Target/AArch64/GISel
Amara Emerson 95ac3d15e9 [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.
For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize
completely if the source is <= 64b. This change adds support for that in
the legalizer. If the source has a pow-2 num elements, then we can do
a tree reduction using the scalar operation in the individual elements.
Otherwise, we just create a sequential chain of operations.

For AArch64, we only need to scalarize if the input is <64b. If it's great than
64b then we can first do a fewElements step to 64b, taking advantage of vector
instructions until we reach the point of scalarization.

I also had to relax the verifier checks for reductions because the intrinsics
support <1 x EltTy> types, which we lower to scalars for GlobalISel.

Differential Revision: https://reviews.llvm.org/D108276
2021-08-19 16:38:52 -07:00
..
AArch64CallLowering.cpp [NFC] Clean up users of AttributeList::hasAttribute() 2021-08-13 11:59:18 -07:00
AArch64CallLowering.h [AArch64][GlobalISel] Fall back if disabling neon/fp in the translator. 2021-03-17 15:08:08 -07:00
AArch64GlobalISelUtils.cpp [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps 2021-05-10 15:40:06 -07:00
AArch64GlobalISelUtils.h [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps 2021-05-10 15:40:06 -07:00
AArch64InstructionSelector.cpp [AArch64][GlobalISel] Fix miscompile of <16 x s8> G_EXTRACT_VECTOR_ELT. 2021-08-19 16:22:32 -07:00
AArch64LegalizerInfo.cpp [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization. 2021-08-19 16:38:52 -07:00
AArch64LegalizerInfo.h [AArch64][GlobalISel] Legalize bswap <2 x i16> 2021-07-17 15:31:15 -07:00
AArch64O0PreLegalizerCombiner.cpp [GISel] Support llvm.memcpy.inline 2021-06-30 12:39:05 -07:00
AArch64PostLegalizerCombiner.cpp [AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT. 2021-07-26 10:58:04 -07:00
AArch64PostLegalizerLowering.cpp [AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128. 2021-07-20 00:04:34 -07:00
AArch64PostSelectOptimize.cpp [various] Remove or use variables which are unused but set. 2021-06-01 15:38:48 -07:00
AArch64PreLegalizerCombiner.cpp [GISel] Support llvm.memcpy.inline 2021-06-30 12:39:05 -07:00
AArch64RegisterBankInfo.cpp [AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes 2021-08-18 13:32:19 -07:00
AArch64RegisterBankInfo.h AArch64: support i128 cmpxchg in GlobalISel. 2021-05-14 10:41:38 +01:00
select-saddo.mir [AArch64][GlobalISel] Select G_SADDO and G_SSUBO 2020-12-08 09:18:28 -08:00
select-ssubo.mir [AArch64][GlobalISel] Select G_SADDO and G_SSUBO 2020-12-08 09:18:28 -08:00