Anton Afanasyev cfb6dfcbd1 [AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG ... Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing TruncInstCombine to reduce bitwidth of expressions containing these instructions. We should be shifting by less than the target bitwidth. Also it is sufficient to require that all truncated bits of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB Alive2 variable-length proof: https://godbolt.org/z/1srE1aqzf => s/32/8/ => https://alive2.llvm.org/ce/z/StwPia Part of https://reviews.llvm.org/D107766 Differential Revision: https://reviews.llvm.org/D108201		2021-08-18 22:20:58 +03:00
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AggressiveInstCombine.cpp	[NewPM] Don't mark AA analyses as preserved	2021-05-18 13:49:03 -07:00
AggressiveInstCombineInternal.h	AggressiveInstCombineInternal.h - reduce unnecessary includes to forward declarations. NFC.	2020-06-26 09:58:20 +01:00
CMakeLists.txt	llvmbuildectomy - replace llvm-build by plain cmake	2020-11-13 10:35:24 +01:00
TruncInstCombine.cpp	[AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG	2021-08-18 22:20:58 +03:00