llvm-project/llvm/test/CodeGen
Amara Emerson 95ac3d15e9 [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.
For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize
completely if the source is <= 64b. This change adds support for that in
the legalizer. If the source has a pow-2 num elements, then we can do
a tree reduction using the scalar operation in the individual elements.
Otherwise, we just create a sequential chain of operations.

For AArch64, we only need to scalarize if the input is <64b. If it's great than
64b then we can first do a fewElements step to 64b, taking advantage of vector
instructions until we reach the point of scalarization.

I also had to relax the verifier checks for reductions because the intrinsics
support <1 x EltTy> types, which we lower to scalars for GlobalISel.

Differential Revision: https://reviews.llvm.org/D108276
2021-08-19 16:38:52 -07:00
..
AArch64 [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization. 2021-08-19 16:38:52 -07:00
AMDGPU [AMDGPU] Add alias.scope metadata to lowered LDS struct 2021-08-19 11:40:30 -07:00
ARC [ARC] Add codegen for count trailing zeros intrinsic for the ARC backend 2021-08-10 12:07:35 -07:00
ARM [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
AVR [AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors' 2021-08-05 10:37:36 +08:00
BPF BPF: avoid NE/EQ loop exit condition 2021-08-04 16:54:16 -07:00
Generic [VP] Add vector-predicated reduction intrinsics 2021-08-17 17:56:35 +01:00
Hexagon [Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs 2021-07-27 18:36:28 -05:00
Inputs
Lanai [Lanai] fix lowering wide returns 2021-08-05 21:08:09 -07:00
M68k [M68k][GloballSel] RegBankSelect implementation 2021-08-10 15:24:43 -07:00
MIR [X86] AVX512FP16 instructions enabling 1/6 2021-08-10 12:46:01 +08:00
MSP430
Mips Revert "Allow rematerialization of virtual reg uses" 2021-08-18 00:12:41 -07:00
NVPTX [NVPTX] Add NVPTX intrinsics for CUDA PTX 6.5 ldmatrix instructions 2021-08-06 16:13:35 -07:00
PowerPC [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
RISCV [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
SPARC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
SystemZ SystemZ: Tidy up a mir test 2021-08-10 13:56:54 -04:00
Thumb Revert "Allow rematerialization of virtual reg uses" 2021-08-18 00:12:41 -07:00
Thumb2 [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
VE [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization. 2021-06-29 11:00:11 -07:00
WebAssembly [WebAssembly] More convert_low and promote_low codegen 2021-08-19 15:37:12 -07:00
WinCFGuard
WinEH
X86 Fix CodeGen/X86/fsafdo_test2.ll fail in release 2021-08-19 16:54:04 +01:00
XCore