276 lines
8.9 KiB
LLVM
276 lines
8.9 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32
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; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32
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; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=ALL,64R6
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=MM32,MM32R3
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefixes=MM32,MM32R6
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; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefix=MM64R6
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define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
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entry:
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; ALL-LABEL: mul_i1:
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; M2: mult $4, $5
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; M2: mflo $[[T0:[0-9]+]]
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; M2: andi $[[T0]], $[[T0]], 1
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; M2: negu $2, $[[T0]]
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; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
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; 32R1-R5: andi $[[T0]], $[[T0]], 1
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; 32R1-R5: negu $2, $[[T0]]
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; 32R6: mul $[[T0:[0-9]+]], $4, $5
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; 32R6: andi $[[T0]], $[[T0]], 1
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; 32R6: negu $2, $[[T0]]
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; M4: mult $4, $5
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; M4: mflo $[[T0:[0-9]+]]
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; M4: andi $[[T0]], $[[T0]], 1
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; M4: negu $2, $[[T0]]
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; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5
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; 64R1-R5: andi $[[T0]], $[[T0]], 1
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; 64R1-R5: negu $2, $[[T0]]
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; 64R6: mul $[[T0:[0-9]+]], $4, $5
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; 64R6: andi $[[T0]], $[[T0]], 1
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; 64R6: negu $2, $[[T0]]
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; MM64R6: mul $[[T0:[0-9]+]], $4, $5
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; MM64R6: andi16 $[[T0]], $[[T0]], 1
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; MM64R6: li16 $[[T1:[0-9]+]], 0
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; MM64R6: subu16 $2, $[[T1]], $[[T0]]
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; MM32: mul $[[T0:[0-9]+]], $4, $5
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; MM32: andi16 $[[T0]], $[[T0]], 1
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; MM32: li16 $[[T1:[0-9]+]], 0
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; MM32: subu16 $2, $[[T1]], $[[T0]]
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%r = mul i1 %a, %b
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ret i1 %r
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}
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define signext i8 @mul_i8(i8 signext %a, i8 signext %b) {
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entry:
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; ALL-LABEL: mul_i8:
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; M2: mult $4, $5
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; M2: mflo $[[T0:[0-9]+]]
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; M2: sll $[[T0]], $[[T0]], 24
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; M2: sra $2, $[[T0]], 24
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; 32R1: mul $[[T0:[0-9]+]], $4, $5
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; 32R1: sll $[[T0]], $[[T0]], 24
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; 32R1: sra $2, $[[T0]], 24
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; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
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; 32R2-R5: seb $2, $[[T0]]
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; 32R6: mul $[[T0:[0-9]+]], $4, $5
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; 32R6: seb $2, $[[T0]]
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; M4: mult $4, $5
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; M4: mflo $[[T0:[0-9]+]]
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; M4: sll $[[T0]], $[[T0]], 24
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; M4: sra $2, $[[T0]], 24
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; 64R1: mul $[[T0:[0-9]+]], $4, $5
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; 64R1: sll $[[T0]], $[[T0]], 24
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; 64R1: sra $2, $[[T0]], 24
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; 64R2: mul $[[T0:[0-9]+]], $4, $5
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; 64R2: seb $2, $[[T0]]
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; 64R6: mul $[[T0:[0-9]+]], $4, $5
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; 64R6: seb $2, $[[T0]]
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; MM64R6: mul $[[T0:[0-9]+]], $4, $5
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; MM64R6: seb $2, $[[T0]]
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; MM32: mul $[[T0:[0-9]+]], $4, $5
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; MM32: seb $2, $[[T0]]
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%r = mul i8 %a, %b
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ret i8 %r
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}
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define signext i16 @mul_i16(i16 signext %a, i16 signext %b) {
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entry:
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; ALL-LABEL: mul_i16:
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; M2: mult $4, $5
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; M2: mflo $[[T0:[0-9]+]]
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; M2: sll $[[T0]], $[[T0]], 16
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; M2: sra $2, $[[T0]], 16
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; 32R1: mul $[[T0:[0-9]+]], $4, $5
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; 32R1: sll $[[T0]], $[[T0]], 16
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; 32R1: sra $2, $[[T0]], 16
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; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
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; 32R2-R5: seh $2, $[[T0]]
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; 32R6: mul $[[T0:[0-9]+]], $4, $5
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; 32R6: seh $2, $[[T0]]
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; M4: mult $4, $5
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; M4: mflo $[[T0:[0-9]+]]
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; M4: sll $[[T0]], $[[T0]], 16
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; M4: sra $2, $[[T0]], 16
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; 64R1: mul $[[T0:[0-9]+]], $4, $5
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; 64R1: sll $[[T0]], $[[T0]], 16
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; 64R1: sra $2, $[[T0]], 16
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; 64R2: mul $[[T0:[0-9]+]], $4, $5
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; 64R2: seh $2, $[[T0]]
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; 64R6: mul $[[T0:[0-9]+]], $4, $5
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; 64R6: seh $2, $[[T0]]
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; MM64R6: mul $[[T0:[0-9]+]], $4, $5
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; MM64R6: seh $2, $[[T0]]
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; MM32: mul $[[T0:[0-9]+]], $4, $5
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; MM32: seh $2, $[[T0]]
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%r = mul i16 %a, %b
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ret i16 %r
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}
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define signext i32 @mul_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: mul_i32:
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; M2: mult $4, $5
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; M2: mflo $2
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; 32R1-R5: mul $2, $4, $5
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; 32R6: mul $2, $4, $5
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; 64R1-R5: mul $2, $4, $5
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; 64R6: mul $2, $4, $5
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; MM64R6: mul $2, $4, $5
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; MM32: mul $2, $4, $5
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%r = mul i32 %a, %b
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ret i32 %r
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}
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define signext i64 @mul_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: mul_i64:
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; M2: mult $4, $7
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; M2: mflo $[[T0:[0-9]+]]
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; M2: mult $5, $6
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; M2: mflo $[[T1:[0-9]+]]
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; M2: multu $5, $7
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; M2: mflo $3
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; M2: mfhi $4
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; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
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; M2: addu $2, $[[T2]], $[[T0]]
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; 32R1-R5: multu $5, $7
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; 32R1-R5: mflo $3
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; 32R1-R5: mfhi $[[T0:[0-9]+]]
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; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6
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; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]]
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; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7
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; 32R1-R5: addu $2, $[[T0]], $[[T2]]
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; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6
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; 32R6: muhu $[[T1:[0-9]+]], $5, $7
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; 32R6: addu $[[T0]], $[[T1]], $[[T0]]
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; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7
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; 32R6: addu $2, $[[T0]], $[[T2]]
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; 32R6-DAG: mul $3, $5, $7
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; M4: dmult $4, $5
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; M4: mflo $2
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; 64R1-R5: dmult $4, $5
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; 64R1-R5: mflo $2
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; 64R6: dmul $2, $4, $5
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; MM64R6: dmul $2, $4, $5
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; MM32R3: multu $[[T0:[0-9]+]], $7
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; MM32R3: mflo $[[T1:[0-9]+]]
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; MM32R3: mfhi $[[T2:[0-9]+]]
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; MM32R3: mul $[[T0]], $[[T0]], $6
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; MM32R3: addu16 $2, $[[T2]], $[[T0]]
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; MM32R3: mul $[[T3:[0-9]+]], $4, $7
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; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]]
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; MM32R6: mul $[[T0:[0-9]+]], $5, $6
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; MM32R6: muhu $[[T1:[0-9]+]], $5, $7
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; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; MM32R6: mul $[[T3:[0-9]+]], $4, $7
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; MM32R6: addu16 $2, $[[T2]], $[[T3]]
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; MM32R6: mul $[[T1]], $5, $7
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%r = mul i64 %a, %b
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ret i64 %r
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}
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define signext i128 @mul_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: mul_i128:
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; GP32: lw $25, %call16(__multi3)($gp)
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; GP64-NOT-R6: dmult $4, $7
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; GP64-NOT-R6: mflo $[[T0:[0-9]+]]
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; GP64-NOT-R6: dmult $5, $6
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; GP64-NOT-R6: mflo $[[T1:[0-9]+]]
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; GP64-NOT-R6: dmultu $5, $7
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; GP64-NOT-R6: mflo $3
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; GP64-NOT-R6: mfhi $[[T2:[0-9]+]]
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; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
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; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
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; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7
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; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
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; 64R6: daddu $2, $[[T1]], $[[T0]]
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; 64R6-DAG: dmul $3, $5, $7
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; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
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; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7
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; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
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; MM64R6: daddu $2, $[[T1]], $[[T0]]
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; MM64R6-DAG: dmul $3, $5, $7
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; MM32: lw $25, %call16(__multi3)($16)
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%r = mul i128 %a, %b
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ret i128 %r
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}
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