274 lines
9.4 KiB
LLVM
274 lines
9.4 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefixes=ALL,M2,M2-M3
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefixes=ALL,SEL,SEL-32
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefixes=ALL,M3,M2-M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: -check-prefixes=ALL,CMOV,CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefixes=ALL,SEL,SEL-64
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; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
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; RUN: -check-prefixes=ALL,MM32R3
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; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
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; RUN: -check-prefixes=ALL,MMR6,MM32R6
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define signext i1 @tst_select_i1_i1(i1 signext %s,
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i1 signext %x, i1 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i1:
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
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; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: [[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
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; MM32R3: move $2, $[[T1]]
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; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
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; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; MMR6: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i1 %x, i1 %y
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ret i1 %r
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}
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define signext i8 @tst_select_i1_i8(i1 signext %s,
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i8 signext %x, i8 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i8:
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
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; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: [[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
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; MM32R3: move $2, $[[T1]]
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; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
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; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; MMR6: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i8 %x, i8 %y
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ret i8 %r
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}
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define signext i32 @tst_select_i1_i32(i1 signext %s,
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i32 signext %x, i32 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i32:
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; M2-M3: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], [[BB0:\$BB[0-9_]+]]
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; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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; M2-M3: nop
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; M2-M3: move $5, $6
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; M2-M3: [[BB0]]:
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; M2-M3: jr $ra
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; M2-M3: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
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; MM32R3: move $2, $[[T1]]
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; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
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; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; MMR6: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i32 %x, i32 %y
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ret i32 %r
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}
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define signext i64 @tst_select_i1_i64(i1 signext %s,
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i64 signext %x, i64 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i64:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: lw $[[T1:[0-9]+]], 16($sp)
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; M2: $[[BB0]]:
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; FIXME: This branch is redundant
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; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
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; M2: nop
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; M2: lw $[[T2:[0-9]+]], 20($sp)
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; M2: $[[BB1]]:
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; M2: move $2, $[[T1]]
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; M2: jr $ra
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; M2: move $3, $[[T2]]
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; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-32: lw $2, 16($sp)
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; CMOV-32: movn $2, $6, $[[T0]]
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; CMOV-32: lw $3, 20($sp)
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; CMOV-32: movn $3, $7, $[[T0]]
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; SEL-32: andi $[[T0:[0-9]+]], $4, 1
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; SEL-32: lw $[[T1:[0-9]+]], 16($sp)
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; SEL-32: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
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; SEL-32: selnez $[[T3:[0-9]+]], $6, $[[T0]]
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; SEL-32: or $2, $[[T3]], $[[T2]]
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; SEL-32: lw $[[T4:[0-9]+]], 20($sp)
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; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
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; SEL-32: selnez $[[T6:[0-9]+]], $7, $[[T0]]
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; SEL-32: or $3, $[[T6]], $[[T5]]
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; M3: andi $[[T0:[0-9]+]], $4, 1
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; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]]
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; M3: nop
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; M3: move $5, $6
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; M3: [[BB0]]:
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; M3: jr $ra
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; M3: move $2, $5
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn $6, $5, $[[T0]]
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; CMOV-64: move $2, $6
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; SEL-64: andi $[[T0:[0-9]+]], $4, 1
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; FIXME: This shift is redundant
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; SEL-64: sll $[[T0]], $[[T0]], 0
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; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL-64: selnez $[[T0]], $5, $[[T0]]
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; SEL-64: or $2, $[[T0]], $[[T1]]
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; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
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; MM32R3: lw $2, 16($sp)
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; MM32R3: movn $2, $6, $[[T0]]
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; MM32R3: lw $3, 20($sp)
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; MM32R3: movn $3, $7, $[[T0]]
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; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
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; MM32R6: lw $[[T2:[0-9]+]], 16($sp)
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; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]]
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; MM32R6: or $2, $[[T1]], $[[T3]]
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; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
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; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
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; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
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; MM32R6: or $3, $[[T6]], $[[T5]]
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%r = select i1 %s, i64 %x, i64 %y
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ret i64 %r
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}
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define i8* @tst_select_word_cst(i8* %a, i8* %b) {
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; ALL-LABEL: tst_select_word_cst:
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; M2: addiu $[[T0:[0-9]+]], $zero, -1
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; M2: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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; M2: bnez $[[T2]], [[BB0:\$BB[0-9_]+]]
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; M2: addiu $2, $zero, 0
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; M2: move $2, $4
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; M2: [[BB0]]:
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; M2: jr $ra
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; M3: daddiu $[[T0:[0-9]+]], $zero, -1
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; M3: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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; M3: bnez $[[T2]], [[BB0:\.LBB[0-9_]+]]
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; M3: daddiu $2, $zero, 0
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; M3: move $2, $4
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; M3: [[BB0]]:
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; M3: jr $ra
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; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
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; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
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; CMOV-32: jr $ra
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; CMOV-32: move $2, $[[T2]]
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; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1
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; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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; SEL-32: jr $ra
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; SEL-32: seleqz $2, $4, $[[T2]]
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; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1
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; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]]
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; CMOV-64: move $2, $[[T2]]
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; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1
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; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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; FIXME: This shift is redundant.
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; SEL-64: sll $[[T2]], $[[T2]], 0
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; SEL-64: seleqz $2, $4, $[[T2]]
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; MM32R3: li16 $[[T0:[0-9]+]], -1
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; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; MM32R3: li16 $[[T2:[0-9]+]], 0
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; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; MM32R3: move $2, $[[T3]]
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; MM32R6: li16 $[[T0:[0-9]+]], -1
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; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
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; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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; MM32R6: seleqz $2, $4, $[[T2]]
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%cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
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%r = select i1 %cmp, i8* %a, i8* null
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ret i8* %r
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}
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