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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 06c5d74090 [RISCV] Remove lowerSPLAT_VECTOR 
This code handles fixed vector SPLAT_VECTOR, but is never called in
any tests.

We only form fixed vector splat vectors for vXi64 on RV32 as part
of DAGCombine. This will be type legalized to SPLAT_VECTOR_PARTS.
So the Custom handling for SPLAT_VECTOR is never needed.

This patch makes SPLAT_VECTOR for vXi64 'Legal' on RV32 so that
DAGCombine will create it, but there's no need for Custom handler.
It will still be type legalized to SPLAT_VECTOR_PARTS.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D121673
 		2022-03-15 08:22:13 -07:00
..
AsmParser [RISCV] add the MC layer support of Zfinx extension 2022-03-02 14:25:19 +08:00
Disassembler [RISCV] add the MC layer support of Zfinx extension 2022-03-02 14:25:19 +08:00
MCTargetDesc [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 2022-03-13 18:06:09 +08:00
TargetInfo Fix shlib builds for all lib/Target/*/TargetInfo libs 2021-10-08 15:21:13 -07:00
CMakeLists.txt [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.h [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.td [RISCV] Support 'generic' as a valid CPU name. 2022-03-09 16:43:22 -08:00
RISCVAsmPrinter.cpp Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVFrameLowering.h Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp [RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values. 2022-01-04 10:13:34 -08:00
RISCVISelDAGToDAG.cpp [RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate. 2022-03-06 19:22:35 -08:00
RISCVISelDAGToDAG.h [RISCV] Select unmasked RVV pseudos in a DAG post-process 2022-02-09 07:50:15 +00:00
RISCVISelLowering.cpp [RISCV] Remove lowerSPLAT_VECTOR 2022-03-15 08:22:13 -07:00
RISCVISelLowering.h [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 2022-03-13 18:06:09 +08:00
RISCVInsertVSETVLI.cpp [RISCV][NFC] Add helper function isVectorConfigInstr to reduce Repeated code. 2022-02-24 05:59:12 +00:00
RISCVInstrFormats.td [RISCV] Add strictfp support for compares. 2022-01-11 20:01:41 -08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Remove Zvamo Extention 2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
RISCVInstrInfo.h [MachineOutliner] NFC: Hide LRU-related stuff behind helper functions 2022-02-16 11:39:07 -08:00
RISCVInstrInfo.td [RISCV] Add tablegen helper classes to create PatFrag to check for one use. NFC 2022-03-10 23:14:21 -08:00
RISCVInstrInfoA.td [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage 2022-02-28 14:02:43 +08:00
RISCVInstrInfoC.td [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets 2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoF.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoM.td [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td [RISCV] Change rvv version to 1.0 and remove ratify notice 2022-02-25 11:38:20 +11:00
RISCVInstrInfoVPseudos.td [RISCV] Optimize vfmv.s.f intrinsic with scalar 0.0 to vmv.s.x with x0. 2022-03-11 10:05:43 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Fold store of vmv.f.s to a vse with VL=1. 2022-03-03 16:35:19 +08:00
RISCVInstrInfoVVLPatterns.td [RISCV] Add isel patterns for masked RISCVISD::FMA_VL with RISCVISD::FNEG_VL. 2022-03-10 10:05:42 -08:00
RISCVInstrInfoZb.td [RISCV] Move GORCIW/GREVIW formation to isel patterns. 2022-03-11 18:02:47 -08:00
RISCVInstrInfoZfh.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoZk.td [RISCV] Adjust some comments. 2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp [Target] Remove redundant member initialization (NFC) 2022-01-06 22:01:44 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
RISCVMachineFunctionInfo.h
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RISCVMergeBaseOffset.cpp Revert "Cleanup codegen includes" 2022-03-10 07:59:22 -05:00
RISCVRedundantCopyElimination.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp [nfc][codegen] Move RegisterBank[Info].h under CodeGen 2022-03-01 21:53:25 -08:00
RISCVRegisterBankInfo.h [nfc][codegen] Move RegisterBank[Info].h under CodeGen 2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp Drop some more global std::maps. NFCI. 2022-03-06 13:28:29 +01:00
RISCVRegisterInfo.h [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td [RISCV] add the MC layer support of Zfinx extension 2022-03-02 14:25:19 +08:00
RISCVSExtWRemoval.cpp [RISCV] Add FMV_X_W and FMV_X_H to RISCVSExtWRemoval. 2022-02-03 09:40:47 -08:00
RISCVSchedRocket.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVSchedule.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVScheduleB.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVScheduleV.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp [RISCV] Support 'generic' as a valid CPU name. 2022-03-09 16:43:22 -08:00
RISCVSubtarget.h [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 2022-03-13 18:06:09 +08:00
RISCVSystemOperands.td [RISCV] Initially support the K-extension instructions on the LLVM MC layer 2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp mark getTargetTransformInfo and getTargetIRAnalysis as const 2022-02-25 14:30:44 -05:00
RISCVTargetMachine.h mark getTargetTransformInfo and getTargetIRAnalysis as const 2022-02-25 14:30:44 -05:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [RISCV] Add basic code modeling for fixed length vector reduction. 2022-03-14 11:04:31 +08:00
RISCVTargetTransformInfo.h [RISCV] Add basic code modeling for fixed length vector reduction. 2022-03-14 11:04:31 +08:00