106 lines
3.6 KiB
C++
106 lines
3.6 KiB
C++
//===--------------------- BottleneckAnalysis.h -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements the bottleneck analysis view.
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///
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/// This view internally observes backend pressure increase events in order to
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/// identify potential sources of bottlenecks.
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///
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/// Example of bottleneck analysis report:
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///
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/// Cycles with backend pressure increase [ 33.40% ]
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/// Throughput Bottlenecks:
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/// Resource Pressure [ 0.52% ]
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/// - JLAGU [ 0.52% ]
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/// Data Dependencies: [ 32.88% ]
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/// - Register Dependencies [ 32.88% ]
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/// - Memory Dependencies [ 0.00% ]
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_BOTTLENECK_ANALYSIS_H
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#define LLVM_TOOLS_LLVM_MCA_BOTTLENECK_ANALYSIS_H
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#include "Views/View.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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namespace mca {
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/// A view that collects and prints a few performance numbers.
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class BottleneckAnalysis : public View {
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const llvm::MCSchedModel &SM;
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unsigned TotalCycles;
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struct BackPressureInfo {
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// Cycles where backpressure increased.
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unsigned PressureIncreaseCycles;
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// Cycles where backpressure increased because of pipeline pressure.
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unsigned ResourcePressureCycles;
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// Cycles where backpressure increased because of data dependencies.
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unsigned DataDependencyCycles;
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// Cycles where backpressure increased because of register dependencies.
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unsigned RegisterDependencyCycles;
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// Cycles where backpressure increased because of memory dependencies.
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unsigned MemoryDependencyCycles;
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};
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BackPressureInfo BPI;
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// Resource pressure distribution. There is an element for every processor
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// resource declared by the scheduling model. Quantities are number of cycles.
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llvm::SmallVector<unsigned, 8> ResourcePressureDistribution;
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// Each processor resource is associated with a so-called processor resource
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// mask. This vector allows to correlate processor resource IDs with processor
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// resource masks. There is exactly one element per each processor resource
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// declared by the scheduling model.
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llvm::SmallVector<uint64_t, 8> ProcResourceMasks;
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// Used to map resource indices to actual processor resource IDs.
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llvm::SmallVector<unsigned, 8> ResIdx2ProcResID;
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// True if resource pressure events were notified during this cycle.
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bool PressureIncreasedBecauseOfResources;
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bool PressureIncreasedBecauseOfDataDependencies;
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// True if throughput was affected by dispatch stalls.
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bool SeenStallCycles;
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// Prints a bottleneck message to OS.
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void printBottleneckHints(llvm::raw_ostream &OS) const;
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public:
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BottleneckAnalysis(const llvm::MCSchedModel &Model);
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void onCycleEnd() override {
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++TotalCycles;
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if (PressureIncreasedBecauseOfResources ||
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PressureIncreasedBecauseOfDataDependencies) {
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++BPI.PressureIncreaseCycles;
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if (PressureIncreasedBecauseOfDataDependencies)
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++BPI.DataDependencyCycles;
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PressureIncreasedBecauseOfResources = false;
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PressureIncreasedBecauseOfDataDependencies = false;
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}
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}
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void onEvent(const HWStallEvent &Event) override { SeenStallCycles = true; }
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void onEvent(const HWPressureEvent &Event) override;
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void printView(llvm::raw_ostream &OS) const override;
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};
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} // namespace mca
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} // namespace llvm
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#endif
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