188 lines
7.8 KiB
C++
188 lines
7.8 KiB
C++
//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Cell SPU uses to lower LLVM code into
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// a selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPU_ISELLOWERING_H
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#define SPU_ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "SPU.h"
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namespace llvm {
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namespace SPUISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Pseudo instructions:
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RET_FLAG, ///< Return with flag, matched by bi instruction
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Hi, ///< High address component (upper 16)
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Lo, ///< Low address component (lower 16)
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PCRelAddr, ///< Program counter relative address
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AFormAddr, ///< A-form address (local store)
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IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
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LDRESULT, ///< Load result (value, chain)
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CALL, ///< CALL instruction
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SHUFB, ///< Vector shuffle (permute)
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SHUFFLE_MASK, ///< Shuffle mask
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CNTB, ///< Count leading ones in bytes
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PREFSLOT2VEC, ///< Promote scalar->vector
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VEC2PREFSLOT, ///< Extract element 0
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SHL_BITS, ///< Shift quad left, by bits
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SHL_BYTES, ///< Shift quad left, by bytes
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SRL_BYTES, ///< Shift quad right, by bytes. Insert zeros.
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VEC_ROTL, ///< Vector rotate left
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VEC_ROTR, ///< Vector rotate right
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ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
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ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
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SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
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SELB, ///< Select bits -> (b & mask) | (a & ~mask)
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// Markers: These aren't used to generate target-dependent nodes, but
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// are used during instruction selection.
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ADD64_MARKER, ///< i64 addition marker
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SUB64_MARKER, ///< i64 subtraction marker
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MUL64_MARKER, ///< i64 multiply marker
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LAST_SPUISD ///< Last user-defined instruction
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};
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}
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//! Utility functions specific to CellSPU:
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namespace SPU {
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SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
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EVT ValueType);
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SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
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EVT ValueType);
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SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
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EVT ValueType);
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SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
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EVT ValueType);
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SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
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EVT ValueType);
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SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
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SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
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const SPUTargetMachine &TM);
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//! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
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SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
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DebugLoc dl);
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}
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class SPUTargetMachine; // forward dec'l.
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class SPUTargetLowering :
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public TargetLowering
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{
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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SPUTargetMachine &SPUTM;
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public:
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//! The venerable constructor
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/*!
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This is where the CellSPU backend sets operation handling (i.e., legal,
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custom, expand or promote.)
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*/
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SPUTargetLowering(SPUTargetMachine &TM);
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//! Get the target machine
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SPUTargetMachine &getSPUTargetMachine() {
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return SPUTM;
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}
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/// getTargetNodeName() - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - Return the ValueType for ISD::SETCC
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virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
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//! Custom lowering hooks
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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//! Custom lowering hook for nodes with illegal result types.
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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unsigned Depth = 0) const;
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ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode.
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virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
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virtual bool isLegalAddressImmediate(GlobalValue *) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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virtual bool isLegalICmpImmediate(int64_t Imm) const;
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virtual bool isLegalAddressingMode(const AddrMode &AM,
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const Type *Ty) const;
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};
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}
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#endif
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