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AsmParser
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[RISCV] Silence unused variable warning in Release builds. NFC.
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2020-06-27 23:24:28 +02:00 |
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Disassembler
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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MCTargetDesc
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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Utils
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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CMakeLists.txt
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[RISCV] Split the pseudo instruction splitting pass
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2020-06-29 14:35:57 +01:00 |
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LLVMBuild.txt
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…
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RISCV.h
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[RISCV] Split the pseudo instruction splitting pass
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2020-06-29 14:35:57 +01:00 |
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RISCV.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVAsmPrinter.cpp
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[RISCV] ELF attribute section for RISC-V.
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2020-03-31 16:16:19 +08:00 |
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RISCVCallLowering.cpp
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…
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RISCVCallLowering.h
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…
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RISCVCallingConv.td
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[RISCV] Rename FPRs and use Register arithmetic
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2019-09-27 15:49:10 +00:00 |
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Split the pseudo instruction splitting pass
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2020-06-29 14:35:57 +01:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Split the pseudo instruction splitting pass
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2020-06-29 14:35:57 +01:00 |
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RISCVFrameLowering.cpp
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[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
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2020-07-01 07:28:11 +00:00 |
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RISCVFrameLowering.h
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CodeGen: Use Register in TargetFrameLowering
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2020-04-07 17:07:44 -04:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp
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2020-04-01 11:30:21 +08:00 |
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RISCVISelLowering.cpp
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[RISCV] Implement Hooks to avoid chaining SELECT
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2020-07-01 11:56:31 +01:00 |
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RISCVISelLowering.h
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[RISCV] Make visibility of overridden methods in RISCVISelLowering match the parent
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2020-06-10 09:16:09 +01:00 |
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RISCVInstrFormats.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVInstrFormatsC.td
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…
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RISCVInstrFormatsV.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVInstrInfo.cpp
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[MachineOutliner] Teach outliner to set live-ins
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2020-04-22 14:19:26 -07:00 |
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RISCVInstrInfo.h
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVInstrInfo.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVInstrInfoA.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoB.td
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[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)
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2020-04-09 18:04:22 +01:00 |
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RISCVInstrInfoC.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoD.td
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[RISCV] Add patterns for checking isnan
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2020-05-02 15:01:04 +01:00 |
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RISCVInstrInfoF.td
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[RISCV] Add patterns for checking isnan
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2020-05-02 15:01:04 +01:00 |
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RISCVInstrInfoM.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoV.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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…
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RISCVMCInstLower.cpp
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…
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RISCVMachineFunctionInfo.h
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[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
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2020-07-01 07:28:11 +00:00 |
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RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp
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Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
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2020-03-20 11:02:50 +01:00 |
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RISCVRegisterBankInfo.h
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Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
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2020-03-20 11:02:50 +01:00 |
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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RISCV: Don't store function in RISCVMachineFunctionInfo
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2020-06-30 16:08:51 -04:00 |
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RISCVRegisterInfo.h
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CodeGen: More conversions to use Register
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2020-04-07 18:54:36 -04:00 |
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RISCVRegisterInfo.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVSchedRocket32.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVSchedRocket64.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVSchedule.td
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[RISCV] Add new SchedRead SchedWrite
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2020-03-10 00:12:27 +08:00 |
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RISCVSubtarget.cpp
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Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
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2020-03-20 11:02:50 +01:00 |
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RISCVSubtarget.h
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVSystemOperands.td
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[RISCV] Assemble/Disassemble v-ext instructions.
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2020-06-28 00:54:07 +08:00 |
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RISCVTargetMachine.cpp
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Revert "[RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2"
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2020-07-01 16:01:40 +01:00 |
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RISCVTargetMachine.h
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[RISCV] Add subtargets initialized with target feature
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2019-12-17 09:34:01 -08:00 |
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RISCVTargetObjectFile.cpp
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[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
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2020-05-21 15:23:29 -07:00 |
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RISCVTargetObjectFile.h
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[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
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2020-05-21 15:23:29 -07:00 |
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RISCVTargetTransformInfo.cpp
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[NFC][CostModel] Add TargetCostKind to relevant APIs
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2020-05-05 10:35:54 +01:00 |
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RISCVTargetTransformInfo.h
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[NFC][CostModel] Add TargetCostKind to relevant APIs
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2020-05-05 10:35:54 +01:00 |
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