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llvm-project/llvm/lib/Target/Hexagon
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David Green be7a107070 [ARM] Teach the Arm cost model that a Shift can be folded into other instructions 
This attempts to teach the cost model in Arm that code such as:
  %s = shl i32 %a, 3
  %a = and i32 %s, %b
Can under Arm or Thumb2 become:
  and r0, r1, r2, lsl #3

So the cost of the shift can essentially be free. To do this without
trying to artificially adjust the cost of the "and" instruction, it
needs to get the users of the shl and check if they are a type of
instruction that the shift can be folded into. And so it needs to have
access to the actual instruction in getArithmeticInstrCost, which if
available is added as an extra parameter much like getCastInstrCost.

We otherwise limit it to shifts with a single user, which should
hopefully handle most of the cases. The list of instruction that the
shift can be folded into include ADC, ADD, AND, BIC, CMP, EOR, MVN, ORR,
ORN, RSB, SBC and SUB. This translates to Add, Sub, And, Or, Xor and
ICmp.

Differential Revision: https://reviews.llvm.org/D70966
 		2019-12-09 10:24:33 +00:00
..
AsmParser [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries" 2019-11-21 10:48:08 -08:00
Disassembler [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries" 2019-11-21 10:48:08 -08:00
MCTargetDesc [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries" 2019-11-21 10:48:08 -08:00
TargetInfo [cmake] Explicitly mark libraries defined in lib/ as "Component Libraries" 2019-11-21 10:48:08 -08:00
BitTracker.cpp Use MCRegister in MCRegisterInfo's interfaces 2019-08-02 20:23:00 +00:00
BitTracker.h
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CMakeLists.txt
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Hexagon.h
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Hexagon.td
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HexagonAsmPrinter.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonAsmPrinter.h Include what you use in HexagonAsmPrinter.h 2019-06-03 11:41:18 +00:00
HexagonBitSimplify.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonBitTracker.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonBitTracker.h
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HexagonBlockRanges.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
HexagonBlockRanges.h
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HexagonBranchRelaxation.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
HexagonCFGOptimizer.cpp
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HexagonCallingConv.td
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HexagonCommonGEP.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonConstExtenders.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonConstPropagation.cpp Reland 'Fixed -Wdeprecated-copy warnings. NFCI.' 2019-11-23 23:09:39 +01:00
HexagonCopyToCombine.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonDepArch.h
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HexagonDepArch.td
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HexagonDepDecoders.inc
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HexagonDepIICHVX.td
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HexagonDepIICScalar.td
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HexagonDepITypes.h
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HexagonDepITypes.td
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HexagonDepInstrFormats.td
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HexagonDepInstrInfo.td
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HexagonDepMapAsm2Intrin.td Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" 2019-09-19 16:26:14 +00:00
HexagonDepMappings.td
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HexagonDepOperands.td Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics" 2019-09-19 16:26:14 +00:00
HexagonDepTimingClasses.h
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HexagonEarlyIfConv.cpp Hexagon - fix uninitialized variable warnings. NFCI. 2019-11-14 14:21:16 +00:00
HexagonExpandCondsets.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonFixupHwLoops.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
HexagonFrameLowering.cpp [Hexagon] Fix vector spill expansion to use proper alignment 2019-11-12 09:43:21 -06:00
HexagonFrameLowering.h Use Align for TFL::TransientStackAlignment 2019-10-21 08:31:25 +00:00
HexagonGenExtract.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonGenInsert.cpp Reland 'Fixed -Wdeprecated-copy warnings. NFCI.' 2019-11-23 23:09:39 +01:00
HexagonGenMux.cpp [Hexagon] Validate the iterators before converting them to mux. 2019-11-14 13:01:16 -06:00
HexagonGenPredicate.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonHardwareLoops.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonHazardRecognizer.cpp
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HexagonHazardRecognizer.h
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HexagonIICHVX.td [Hexagon] Avoid creating 5-instruction packets with vgather pseudos 2019-03-06 17:43:50 +00:00
HexagonIICScalar.td
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HexagonISelDAGToDAG.cpp [Hexagon] Update PS_aligna with max stack alignment once isel completes 2019-11-12 11:47:29 -06:00
HexagonISelDAGToDAG.h [Hexagon] Update PS_aligna with max stack alignment once isel completes 2019-11-12 11:47:29 -06:00
HexagonISelDAGToDAGHVX.cpp
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HexagonISelLowering.cpp DAG: Add function context to isFMAFasterThanFMulAndFAdd 2019-11-19 19:25:26 +05:30
HexagonISelLowering.h DAG: Add function context to isFMAFasterThanFMulAndFAdd 2019-11-19 19:25:26 +05:30
HexagonISelLoweringHVX.cpp [Hexagon] Generate vector min/max for HVX 2019-08-15 16:13:17 +00:00
HexagonInstrFormats.td
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HexagonInstrFormatsV5.td
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HexagonInstrFormatsV60.td
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HexagonInstrFormatsV65.td
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HexagonInstrInfo.cpp [Hexagon] Fix vector spill expansion to use proper alignment 2019-11-12 09:43:21 -06:00
HexagonInstrInfo.h Use MCRegister in copyPhysReg 2019-11-11 14:42:33 +05:30
HexagonIntrinsics.td [Hexagon] Remove incorrect intrinsic definition and invalid testcase 2019-11-21 09:18:15 -06:00
HexagonIntrinsicsV5.td
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HexagonIntrinsicsV60.td
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HexagonLoopIdiomRecognition.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonMCInstLower.cpp
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HexagonMachineFunctionInfo.cpp
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HexagonMachineFunctionInfo.h
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HexagonMachineScheduler.cpp
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HexagonMachineScheduler.h
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HexagonMapAsm2IntrinV62.gen.td
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HexagonMapAsm2IntrinV65.gen.td
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HexagonNewValueJump.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonOperands.td
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HexagonOptAddrMode.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonOptimizeSZextends.cpp
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HexagonPatterns.td Fix pattern error for S2_tstbit_i instruction 2019-10-30 11:21:48 -05:00
HexagonPatternsHVX.td [Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX 2019-09-23 14:33:27 +00:00
HexagonPatternsV65.td
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HexagonPeephole.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonPseudo.td [Hexagon] Fix vector spill expansion to use proper alignment 2019-11-12 09:43:21 -06:00
HexagonRDFOpt.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonRegisterInfo.cpp [Hexagon] Fix vector spill expansion to use proper alignment 2019-11-12 09:43:21 -06:00
HexagonRegisterInfo.h CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
HexagonRegisterInfo.td
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HexagonSchedule.td
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HexagonScheduleV5.td
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HexagonScheduleV55.td
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HexagonScheduleV60.td
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HexagonScheduleV62.td
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HexagonScheduleV65.td
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HexagonScheduleV66.td
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HexagonSelectionDAGInfo.cpp
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HexagonSelectionDAGInfo.h
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HexagonSplitConst32AndConst64.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonSplitDouble.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
HexagonStoreWidening.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonSubtarget.cpp Use a bit of relaxed constexpr to make FeatureBitset costant intializable 2019-08-24 15:02:44 +00:00
HexagonSubtarget.h [SVE][MVT] Fixed-length vector MVT ranges 2019-09-17 10:19:23 +00:00
HexagonTargetMachine.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
HexagonTargetMachine.h
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HexagonTargetObjectFile.cpp OpaquePtr: switch to GlobalValue::getValueType in a few places. NFC. 2019-07-11 13:13:02 +00:00
HexagonTargetObjectFile.h
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HexagonTargetStreamer.h
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HexagonTargetTransformInfo.cpp [ARM] Teach the Arm cost model that a Shift can be folded into other instructions 2019-12-09 10:24:33 +00:00
HexagonTargetTransformInfo.h [ARM] Teach the Arm cost model that a Shift can be folded into other instructions 2019-12-09 10:24:33 +00:00
HexagonVExtract.cpp [Hexagon] Handle stack realignment in hexagon-vextract 2019-11-12 09:43:21 -06:00
HexagonVLIWPacketizer.cpp Hexagon - fix uninitialized variable warnings. NFCI. 2019-11-14 14:21:16 +00:00
HexagonVLIWPacketizer.h Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
HexagonVectorLoopCarriedReuse.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
HexagonVectorPrint.cpp
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LLVMBuild.txt
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RDFCopy.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
RDFCopy.h
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RDFDeadCode.cpp Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
RDFDeadCode.h
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RDFGraph.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RDFGraph.h Hexagon RDF: Replace function template (plus explicit specializations) with non-template overloads 2019-03-11 23:10:33 +00:00
RDFLiveness.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RDFLiveness.h Hexagon RDF: Replace function template (plus explicit specializations) with non-template overloads 2019-03-11 23:10:33 +00:00
RDFRegisters.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
RDFRegisters.h Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00