llvm-project/llvm/test/CodeGen
Mikhail Maltsev e6d3261c67 [ARM][MVE] Refactor complex vector intrinsics [NFCI]
Summary:
This patch refactors instruction selection of the complex vector
addition, multiplication and multiply-add intrinsics, so that it is
now based on TableGen patterns rather than C++ code.

It also changes the first parameter (halving vs non-halving) of the
arm_mve_vcaddq IR intrinsic to match the corresponding instruction
encoding, hence it requires some changes in the tests.

The patch addresses David's comment in https://reviews.llvm.org/D71190

Reviewers: dmgreen, ostannard, simon_tatham, MarkMurrayARM

Reviewed By: dmgreen

Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D71245
2019-12-10 16:21:52 +00:00
..
AArch64 [AArch64] Fix issues with large arrays on stack 2019-12-10 11:44:41 +00:00
AMDGPU [MBP] Avoid tail duplication if it can't bring benefit 2019-12-06 09:53:53 -08:00
ARC
ARM [LegalizeTypes] Bugfixes for big-endian targets when handling BITCASTs 2019-12-10 11:22:35 +01:00
AVR
BPF [BPF] Support to emit debugInfo for extern variables 2019-12-09 21:53:29 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [ModuloSchedule] Fix a bug in experimental expander 2019-11-23 16:01:47 -08:00
Inputs
Lanai
MIR [llvm] Fixing MIRVRegNamerUtils to properly handle 2+ MachineBasicBlocks. 2019-12-04 18:36:08 -05:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips Handle BUNDLE instructions in MipsAsmPrinter 2019-12-04 11:30:00 +00:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [BUG-FIX][XCOFF] fixed a bug of XCOFFObjectFile.cpp when there is padding at the last csect of a sections 2019-12-10 11:14:49 -05:00
RISCV [RISCV] Fix mir-target-flags.ll 2019-12-09 13:51:08 +00:00
SPARC Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that 2019-12-03 11:21:52 +01:00
SystemZ [FPEnv] Constrained FCmp intrinsics 2019-12-07 11:28:39 +01:00
Thumb Revert "ARM-Darwin: keep the frame register reserved even if not updated." 2019-12-06 10:59:26 -08:00
Thumb2 [ARM][MVE] Refactor complex vector intrinsics [NFCI] 2019-12-10 16:21:52 +00:00
WebAssembly [WebAssembly] Fix miscompile of select with and 2019-11-15 16:22:01 -08:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH
X86 add support for strict operation fpextend/fpround/fsqrt on X86 backend 2019-12-10 09:04:28 +08:00
XCore