568 lines
20 KiB
C++
568 lines
20 KiB
C++
//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MachineValueType.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Printable.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <utility>
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#define DEBUG_TYPE "target-reg-info"
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using namespace llvm;
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static cl::opt<unsigned>
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HugeSizeForSplit("huge-size-for-split", cl::Hidden,
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cl::desc("A threshold of live range size which may cause "
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"high compile time cost in global splitting."),
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cl::init(5000));
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TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
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regclass_iterator RCB, regclass_iterator RCE,
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const char *const *SRINames,
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const LaneBitmask *SRILaneMasks,
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LaneBitmask SRICoveringLanes,
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const RegClassInfo *const RCIs,
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unsigned Mode)
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: InfoDesc(ID), SubRegIndexNames(SRINames),
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SubRegIndexLaneMasks(SRILaneMasks),
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RegClassBegin(RCB), RegClassEnd(RCE),
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CoveringLanes(SRICoveringLanes),
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RCInfos(RCIs), HwMode(Mode) {
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}
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TargetRegisterInfo::~TargetRegisterInfo() = default;
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bool TargetRegisterInfo::shouldRegionSplitForVirtReg(
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const MachineFunction &MF, const LiveInterval &VirtReg) const {
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
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if (MI && TII->isTriviallyReMaterializable(*MI) &&
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VirtReg.size() > HugeSizeForSplit)
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return false;
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return true;
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}
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void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet,
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MCRegister Reg) const {
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for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
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RegisterSet.set(*AI);
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}
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bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
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ArrayRef<MCPhysReg> Exceptions) const {
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// Check that all super registers of reserved regs are reserved as well.
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BitVector Checked(getNumRegs());
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for (unsigned Reg : RegisterSet.set_bits()) {
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if (Checked[Reg])
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continue;
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for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
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if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
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dbgs() << "Error: Super register " << printReg(*SR, this)
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<< " of reserved register " << printReg(Reg, this)
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<< " is not reserved.\n";
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return false;
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}
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// We transitively check superregs. So we can remember this for later
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// to avoid compiletime explosion in deep register hierarchies.
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Checked.set(*SR);
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}
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}
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return true;
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}
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namespace llvm {
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Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
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unsigned SubIdx, const MachineRegisterInfo *MRI) {
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return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
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if (!Reg)
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OS << "$noreg";
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else if (Register::isStackSlot(Reg))
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OS << "SS#" << Register::stackSlot2Index(Reg);
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else if (Register::isVirtualRegister(Reg)) {
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StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
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if (Name != "") {
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OS << '%' << Name;
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} else {
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OS << '%' << Register::virtReg2Index(Reg);
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}
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} else if (!TRI)
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OS << '$' << "physreg" << Reg;
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else if (Reg < TRI->getNumRegs()) {
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OS << '$';
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printLowerCase(TRI->getName(Reg), OS);
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} else
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llvm_unreachable("Register kind is unsupported.");
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if (SubIdx) {
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if (TRI)
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OS << ':' << TRI->getSubRegIndexName(SubIdx);
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else
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OS << ":sub(" << SubIdx << ')';
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}
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});
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}
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Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
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return Printable([Unit, TRI](raw_ostream &OS) {
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// Generic printout when TRI is missing.
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if (!TRI) {
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OS << "Unit~" << Unit;
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return;
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}
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// Check for invalid register units.
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if (Unit >= TRI->getNumRegUnits()) {
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OS << "BadUnit~" << Unit;
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return;
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}
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// Normal units have at least one root.
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MCRegUnitRootIterator Roots(Unit, TRI);
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assert(Roots.isValid() && "Unit has no roots.");
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OS << TRI->getName(*Roots);
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for (++Roots; Roots.isValid(); ++Roots)
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OS << '~' << TRI->getName(*Roots);
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});
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}
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Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
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return Printable([Unit, TRI](raw_ostream &OS) {
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if (Register::isVirtualRegister(Unit)) {
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OS << '%' << Register::virtReg2Index(Unit);
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} else {
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OS << printRegUnit(Unit, TRI);
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}
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});
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}
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Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
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if (RegInfo.getRegClassOrNull(Reg))
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OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
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else if (RegInfo.getRegBankOrNull(Reg))
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OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
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else {
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OS << "_";
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assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
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"Generic registers must have a valid type");
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}
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});
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}
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} // end namespace llvm
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/// getAllocatableClass - Return the maximal subclass of the given register
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/// class that is alloctable, or NULL.
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const TargetRegisterClass *
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TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
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if (!RC || RC->isAllocatable())
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return RC;
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for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
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++It) {
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const TargetRegisterClass *SubRC = getRegClass(It.getID());
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if (SubRC->isAllocatable())
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return SubRC;
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}
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return nullptr;
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}
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/// getMinimalPhysRegClass - Returns the Register Class of a physical
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/// register of the given type, picking the most sub register class of
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/// the right type that contains this physreg.
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const TargetRegisterClass *
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TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const {
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assert(Register::isPhysicalRegister(reg) &&
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"reg must be a physical register");
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// Pick the most sub register class of the right type that contains
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// this physreg.
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const TargetRegisterClass* BestRC = nullptr;
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for (const TargetRegisterClass* RC : regclasses()) {
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if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
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RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
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BestRC = RC;
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}
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assert(BestRC && "Couldn't find the register class");
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return BestRC;
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}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(const MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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assert(RC->isAllocatable() && "invalid for nonallocatable sets");
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ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
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for (unsigned i = 0; i != Order.size(); ++i)
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R.set(Order[i]);
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}
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BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(getNumRegs());
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if (RC) {
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// A register class with no allocatable subclass returns an empty set.
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const TargetRegisterClass *SubClass = getAllocatableClass(RC);
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if (SubClass)
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getAllocatableSetForRC(MF, SubClass, Allocatable);
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} else {
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for (const TargetRegisterClass *C : regclasses())
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if (C->isAllocatable())
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getAllocatableSetForRC(MF, C, Allocatable);
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}
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// Mask out the reserved registers
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BitVector Reserved = getReservedRegs(MF);
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Allocatable &= Reserved.flip();
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return Allocatable;
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}
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static inline
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const TargetRegisterClass *firstCommonClass(const uint32_t *A,
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const uint32_t *B,
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const TargetRegisterInfo *TRI) {
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for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
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if (unsigned Common = *A++ & *B++)
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return TRI->getRegClass(I + countTrailingZeros(Common));
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return nullptr;
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}
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const TargetRegisterClass *
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TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B) const {
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// First take care of the trivial cases.
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if (A == B)
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return A;
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if (!A || !B)
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return nullptr;
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// Register classes are ordered topologically, so the largest common
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// sub-class it the common sub-class with the smallest ID.
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return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
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}
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const TargetRegisterClass *
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TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const {
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assert(A && B && "Missing register class");
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assert(Idx && "Bad sub-register index");
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// Find Idx in the list of super-register indices.
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for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
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if (RCI.getSubReg() == Idx)
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// The bit mask contains all register classes that are projected into B
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// by Idx. Find a class that is also a sub-class of A.
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return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
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return nullptr;
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}
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const TargetRegisterClass *TargetRegisterInfo::
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getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
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const TargetRegisterClass *RCB, unsigned SubB,
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unsigned &PreA, unsigned &PreB) const {
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assert(RCA && SubA && RCB && SubB && "Invalid arguments");
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// Search all pairs of sub-register indices that project into RCA and RCB
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// respectively. This is quadratic, but usually the sets are very small. On
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// most targets like X86, there will only be a single sub-register index
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// (e.g., sub_16bit projecting into GR16).
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//
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// The worst case is a register class like DPR on ARM.
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// We have indices dsub_0..dsub_7 projecting into that class.
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//
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// It is very common that one register class is a sub-register of the other.
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// Arrange for RCA to be the larger register so the answer will be found in
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// the first iteration. This makes the search linear for the most common
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// case.
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const TargetRegisterClass *BestRC = nullptr;
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unsigned *BestPreA = &PreA;
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unsigned *BestPreB = &PreB;
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if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
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std::swap(RCA, RCB);
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std::swap(SubA, SubB);
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std::swap(BestPreA, BestPreB);
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}
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// Also terminate the search one we have found a register class as small as
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// RCA.
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unsigned MinSize = getRegSizeInBits(*RCA);
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for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
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unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
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for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
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// Check if a common super-register class exists for this index pair.
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const TargetRegisterClass *RC =
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firstCommonClass(IA.getMask(), IB.getMask(), this);
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if (!RC || getRegSizeInBits(*RC) < MinSize)
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continue;
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// The indexes must compose identically: PreA+SubA == PreB+SubB.
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unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
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if (FinalA != FinalB)
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continue;
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// Is RC a better candidate than BestRC?
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if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
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continue;
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// Yes, RC is the smallest super-register seen so far.
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BestRC = RC;
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*BestPreA = IA.getSubReg();
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*BestPreB = IB.getSubReg();
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// Bail early if we reached MinSize. We won't find a better candidate.
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if (getRegSizeInBits(*BestRC) == MinSize)
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return BestRC;
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}
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}
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return BestRC;
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}
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/// Check if the registers defined by the pair (RegisterClass, SubReg)
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/// share the same register file.
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static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
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const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) {
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// Same register class.
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if (DefRC == SrcRC)
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return true;
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// Both operands are sub registers. Check if they share a register class.
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unsigned SrcIdx, DefIdx;
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if (SrcSubReg && DefSubReg) {
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return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
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SrcIdx, DefIdx) != nullptr;
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}
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// At most one of the register is a sub register, make it Src to avoid
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// duplicating the test.
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if (!SrcSubReg) {
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std::swap(DefSubReg, SrcSubReg);
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std::swap(DefRC, SrcRC);
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}
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// One of the register is a sub register, check if we can get a superclass.
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if (SrcSubReg)
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return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
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// Plain copy.
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return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
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}
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bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) const {
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// If this source does not incur a cross register bank copy, use it.
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return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
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}
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// Compute target-independent register allocator hints to help eliminate copies.
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bool TargetRegisterInfo::getRegAllocationHints(
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Register VirtReg, ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
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const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
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MRI.getRegAllocationHints(VirtReg);
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SmallSet<Register, 32> HintedRegs;
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// First hint may be a target hint.
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bool Skip = (Hints_MRI.first != 0);
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for (auto Reg : Hints_MRI.second) {
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if (Skip) {
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Skip = false;
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continue;
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}
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// Target-independent hints are either a physical or a virtual register.
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Register Phys = Reg;
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if (VRM && Phys.isVirtual())
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Phys = VRM->getPhys(Phys);
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// Don't add the same reg twice (Hints_MRI may contain multiple virtual
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// registers allocated to the same physreg).
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if (!HintedRegs.insert(Phys).second)
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continue;
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// Check that Phys is a valid hint in VirtReg's register class.
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if (!Phys.isPhysical())
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continue;
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if (MRI.isReserved(Phys))
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continue;
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// Check that Phys is in the allocation order. We shouldn't heed hints
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// from VirtReg's register class if they aren't in the allocation order. The
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// target probably has a reason for removing the register.
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if (!is_contained(Order, Phys))
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continue;
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// All clear, tell the register allocator to prefer this register.
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Hints.push_back(Phys);
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}
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return false;
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}
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bool TargetRegisterInfo::isCalleeSavedPhysReg(
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MCRegister PhysReg, const MachineFunction &MF) const {
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if (PhysReg == 0)
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return false;
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const uint32_t *callerPreservedRegs =
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getCallPreservedMask(MF, MF.getFunction().getCallingConv());
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if (callerPreservedRegs) {
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assert(Register::isPhysicalRegister(PhysReg) &&
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"Expected physical register");
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return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
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}
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return false;
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}
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bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
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return !MF.getFunction().hasFnAttribute("no-realign-stack");
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}
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bool TargetRegisterInfo::needsStackRealignment(
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const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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const Function &F = MF.getFunction();
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Align StackAlign = TFI->getStackAlign();
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bool requiresRealignment = ((MFI.getMaxAlign() > StackAlign) ||
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F.hasFnAttribute(Attribute::StackAlignment));
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if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
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if (canRealignStack(MF))
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return true;
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LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName()
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<< "\n");
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}
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return false;
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}
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bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
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const uint32_t *mask1) const {
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unsigned N = (getNumRegs()+31) / 32;
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for (unsigned I = 0; I < N; ++I)
|
|
if ((mask0[I] & mask1[I]) != mask0[I])
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
unsigned
|
|
TargetRegisterInfo::getRegSizeInBits(Register Reg,
|
|
const MachineRegisterInfo &MRI) const {
|
|
const TargetRegisterClass *RC{};
|
|
if (Reg.isPhysical()) {
|
|
// The size is not directly available for physical registers.
|
|
// Instead, we need to access a register class that contains Reg and
|
|
// get the size of that register class.
|
|
RC = getMinimalPhysRegClass(Reg);
|
|
} else {
|
|
LLT Ty = MRI.getType(Reg);
|
|
unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
|
|
// If Reg is not a generic register, query the register class to
|
|
// get its size.
|
|
if (RegSize)
|
|
return RegSize;
|
|
// Since Reg is not a generic register, it must have a register class.
|
|
RC = MRI.getRegClass(Reg);
|
|
}
|
|
assert(RC && "Unable to deduce the register class");
|
|
return getRegSizeInBits(*RC);
|
|
}
|
|
|
|
Register
|
|
TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
|
|
const MachineRegisterInfo *MRI) const {
|
|
while (true) {
|
|
const MachineInstr *MI = MRI->getVRegDef(SrcReg);
|
|
if (!MI->isCopyLike())
|
|
return SrcReg;
|
|
|
|
Register CopySrcReg;
|
|
if (MI->isCopy())
|
|
CopySrcReg = MI->getOperand(1).getReg();
|
|
else {
|
|
assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
|
|
CopySrcReg = MI->getOperand(2).getReg();
|
|
}
|
|
|
|
if (!CopySrcReg.isVirtual())
|
|
return CopySrcReg;
|
|
|
|
SrcReg = CopySrcReg;
|
|
}
|
|
}
|
|
|
|
void TargetRegisterInfo::getOffsetOpcodes(
|
|
const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
|
|
assert(!Offset.getScalable() && "Scalable offsets are not handled");
|
|
DIExpression::appendOffset(Ops, Offset.getFixed());
|
|
}
|
|
|
|
DIExpression *
|
|
TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
|
|
unsigned PrependFlags,
|
|
const StackOffset &Offset) const {
|
|
assert((PrependFlags &
|
|
~(DIExpression::DerefBefore | DIExpression::DerefAfter |
|
|
DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
|
|
"Unsupported prepend flag");
|
|
SmallVector<uint64_t, 16> OffsetExpr;
|
|
if (PrependFlags & DIExpression::DerefBefore)
|
|
OffsetExpr.push_back(dwarf::DW_OP_deref);
|
|
getOffsetOpcodes(Offset, OffsetExpr);
|
|
if (PrependFlags & DIExpression::DerefAfter)
|
|
OffsetExpr.push_back(dwarf::DW_OP_deref);
|
|
return DIExpression::prependOpcodes(Expr, OffsetExpr,
|
|
PrependFlags & DIExpression::StackValue,
|
|
PrependFlags & DIExpression::EntryValue);
|
|
}
|
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
|
LLVM_DUMP_METHOD
|
|
void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
|
|
const TargetRegisterInfo *TRI) {
|
|
dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
|
|
}
|
|
#endif
|