1268 lines
47 KiB
C++
1268 lines
47 KiB
C++
//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler Emitter.
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// It contains the implementation of a single recognizable instruction.
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// Documentation for the disassembler emitter in general can be found in
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// X86DisassemblerEmitter.h.
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//
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//===----------------------------------------------------------------------===//
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#include "X86RecognizableInstr.h"
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#include "X86DisassemblerShared.h"
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#include "X86ModRMFilters.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <string>
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using namespace llvm;
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using namespace X86Disassembler;
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/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
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/// Useful for switch statements and the like.
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///
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/// @param init - A reference to the BitsInit to be decoded.
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/// @return - The field, with the first bit in the BitsInit as the lowest
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/// order bit.
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static uint8_t byteFromBitsInit(BitsInit &init) {
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int width = init.getNumBits();
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assert(width <= 8 && "Field is too large for uint8_t!");
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int index;
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uint8_t mask = 0x01;
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uint8_t ret = 0;
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for (index = 0; index < width; index++) {
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if (cast<BitInit>(init.getBit(index))->getValue())
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ret |= mask;
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mask <<= 1;
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}
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return ret;
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}
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/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
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/// name of the field.
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///
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/// @param rec - The record from which to extract the value.
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/// @param name - The name of the field in the record.
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/// @return - The field, as translated by byteFromBitsInit().
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static uint8_t byteFromRec(const Record* rec, StringRef name) {
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BitsInit* bits = rec->getValueAsBitsInit(name);
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return byteFromBitsInit(*bits);
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}
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RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid) {
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UID = uid;
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Rec = insn.TheDef;
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Name = std::string(Rec->getName());
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Spec = &tables.specForUID(UID);
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if (!Rec->isSubClassOf("X86Inst")) {
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ShouldBeEmitted = false;
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return;
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}
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OpPrefix = byteFromRec(Rec, "OpPrefixBits");
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OpMap = byteFromRec(Rec, "OpMapBits");
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Opcode = byteFromRec(Rec, "Opcode");
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Form = byteFromRec(Rec, "FormBits");
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Encoding = byteFromRec(Rec, "OpEncBits");
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OpSize = byteFromRec(Rec, "OpSizeBits");
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AdSize = byteFromRec(Rec, "AdSizeBits");
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HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
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HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
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HasVEX_W = Rec->getValueAsBit("HasVEX_W");
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IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W");
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IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
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HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
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HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
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HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
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HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
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IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
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ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
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CD8_Scale = byteFromRec(Rec, "CD8_Scale");
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Name = std::string(Rec->getName());
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Operands = &insn.Operands.OperandList;
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HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
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EncodeRC = HasEVEX_B &&
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(Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
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// Check for 64-bit inst which does not require REX
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Is32Bit = false;
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Is64Bit = false;
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// FIXME: Is there some better way to check for In64BitMode?
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std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
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for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
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if (Predicates[i]->getName().contains("Not64Bit") ||
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Predicates[i]->getName().contains("In32Bit")) {
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Is32Bit = true;
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break;
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}
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if (Predicates[i]->getName().contains("In64Bit")) {
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Is64Bit = true;
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break;
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}
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}
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if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
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ShouldBeEmitted = false;
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return;
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}
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ShouldBeEmitted = true;
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}
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void RecognizableInstr::processInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid)
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{
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// Ignore "asm parser only" instructions.
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if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
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return;
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RecognizableInstr recogInstr(tables, insn, uid);
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if (recogInstr.shouldBeEmitted()) {
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recogInstr.emitInstructionSpecifier();
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recogInstr.emitDecodePath(tables);
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}
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}
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#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
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(HasEVEX_K && HasEVEX_B ? n##_K_B : \
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(HasEVEX_KZ ? n##_KZ : \
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(HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
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InstructionContext RecognizableInstr::insnContext() const {
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InstructionContext insnContext;
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if (Encoding == X86Local::EVEX) {
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if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
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errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
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llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
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}
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// VEX_L & VEX_W
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if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) {
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if (OpPrefix == X86Local::PD)
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insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
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else if (OpPrefix == X86Local::XS)
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insnContext = EVEX_KB(IC_EVEX_L_W_XS);
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else if (OpPrefix == X86Local::XD)
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insnContext = EVEX_KB(IC_EVEX_L_W_XD);
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else if (OpPrefix == X86Local::PS)
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insnContext = EVEX_KB(IC_EVEX_L_W);
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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} else if (!EncodeRC && HasVEX_LPrefix) {
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// VEX_L
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if (OpPrefix == X86Local::PD)
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insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
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else if (OpPrefix == X86Local::XS)
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insnContext = EVEX_KB(IC_EVEX_L_XS);
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else if (OpPrefix == X86Local::XD)
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insnContext = EVEX_KB(IC_EVEX_L_XD);
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else if (OpPrefix == X86Local::PS)
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insnContext = EVEX_KB(IC_EVEX_L);
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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} else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) {
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// EVEX_L2 & VEX_W
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if (OpPrefix == X86Local::PD)
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insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
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else if (OpPrefix == X86Local::XS)
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insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
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else if (OpPrefix == X86Local::XD)
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insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
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else if (OpPrefix == X86Local::PS)
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insnContext = EVEX_KB(IC_EVEX_L2_W);
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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} else if (!EncodeRC && HasEVEX_L2Prefix) {
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// EVEX_L2
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if (OpPrefix == X86Local::PD)
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insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
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else if (OpPrefix == X86Local::XD)
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insnContext = EVEX_KB(IC_EVEX_L2_XD);
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else if (OpPrefix == X86Local::XS)
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insnContext = EVEX_KB(IC_EVEX_L2_XS);
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else if (OpPrefix == X86Local::PS)
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insnContext = EVEX_KB(IC_EVEX_L2);
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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}
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else if (HasVEX_W) {
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// VEX_W
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if (OpPrefix == X86Local::PD)
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insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
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else if (OpPrefix == X86Local::XS)
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insnContext = EVEX_KB(IC_EVEX_W_XS);
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else if (OpPrefix == X86Local::XD)
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insnContext = EVEX_KB(IC_EVEX_W_XD);
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else if (OpPrefix == X86Local::PS)
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insnContext = EVEX_KB(IC_EVEX_W);
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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}
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// No L, no W
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else if (OpPrefix == X86Local::PD)
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insnContext = EVEX_KB(IC_EVEX_OPSIZE);
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else if (OpPrefix == X86Local::XD)
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insnContext = EVEX_KB(IC_EVEX_XD);
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else if (OpPrefix == X86Local::XS)
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insnContext = EVEX_KB(IC_EVEX_XS);
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else if (OpPrefix == X86Local::PS)
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insnContext = EVEX_KB(IC_EVEX);
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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/// eof EVEX
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} else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
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if (HasVEX_LPrefix && HasVEX_W) {
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if (OpPrefix == X86Local::PD)
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insnContext = IC_VEX_L_W_OPSIZE;
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else if (OpPrefix == X86Local::XS)
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insnContext = IC_VEX_L_W_XS;
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else if (OpPrefix == X86Local::XD)
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insnContext = IC_VEX_L_W_XD;
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else if (OpPrefix == X86Local::PS)
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insnContext = IC_VEX_L_W;
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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} else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
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insnContext = IC_VEX_L_OPSIZE;
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else if (OpPrefix == X86Local::PD && HasVEX_W)
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insnContext = IC_VEX_W_OPSIZE;
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else if (OpPrefix == X86Local::PD && Is64Bit &&
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AdSize == X86Local::AdSize32)
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insnContext = IC_64BIT_VEX_OPSIZE_ADSIZE;
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else if (OpPrefix == X86Local::PD && Is64Bit)
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insnContext = IC_64BIT_VEX_OPSIZE;
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else if (OpPrefix == X86Local::PD)
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insnContext = IC_VEX_OPSIZE;
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else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
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insnContext = IC_VEX_L_XS;
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else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
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insnContext = IC_VEX_L_XD;
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else if (HasVEX_W && OpPrefix == X86Local::XS)
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insnContext = IC_VEX_W_XS;
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else if (HasVEX_W && OpPrefix == X86Local::XD)
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insnContext = IC_VEX_W_XD;
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else if (HasVEX_W && OpPrefix == X86Local::PS)
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insnContext = IC_VEX_W;
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else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
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insnContext = IC_VEX_L;
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else if (OpPrefix == X86Local::XD)
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insnContext = IC_VEX_XD;
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else if (OpPrefix == X86Local::XS)
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insnContext = IC_VEX_XS;
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else if (OpPrefix == X86Local::PS)
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insnContext = IC_VEX;
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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} else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
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if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
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insnContext = IC_64BIT_REXW_OPSIZE;
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else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
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insnContext = IC_64BIT_REXW_ADSIZE;
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else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
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insnContext = IC_64BIT_XD_OPSIZE;
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else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
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insnContext = IC_64BIT_XS_OPSIZE;
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else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
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insnContext = IC_64BIT_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
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insnContext = IC_64BIT_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
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insnContext = IC_64BIT_OPSIZE;
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else if (AdSize == X86Local::AdSize32)
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insnContext = IC_64BIT_ADSIZE;
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else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
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insnContext = IC_64BIT_REXW_XS;
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else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
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insnContext = IC_64BIT_REXW_XD;
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else if (OpPrefix == X86Local::XD)
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insnContext = IC_64BIT_XD;
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else if (OpPrefix == X86Local::XS)
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insnContext = IC_64BIT_XS;
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else if (HasREX_WPrefix)
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insnContext = IC_64BIT_REXW;
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else
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insnContext = IC_64BIT;
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} else {
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if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
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insnContext = IC_XD_OPSIZE;
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else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
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insnContext = IC_XS_OPSIZE;
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else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
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insnContext = IC_XD_ADSIZE;
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else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
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insnContext = IC_XS_ADSIZE;
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else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
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insnContext = IC_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
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insnContext = IC_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
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insnContext = IC_OPSIZE;
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else if (AdSize == X86Local::AdSize16)
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insnContext = IC_ADSIZE;
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else if (OpPrefix == X86Local::XD)
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insnContext = IC_XD;
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else if (OpPrefix == X86Local::XS)
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insnContext = IC_XS;
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else
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insnContext = IC;
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}
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return insnContext;
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}
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void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
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// The scaling factor for AVX512 compressed displacement encoding is an
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// instruction attribute. Adjust the ModRM encoding type to include the
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// scale for compressed displacement.
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if ((encoding != ENCODING_RM &&
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encoding != ENCODING_VSIB &&
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encoding != ENCODING_SIB) ||CD8_Scale == 0)
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return;
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encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
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assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
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(encoding == ENCODING_SIB) ||
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(encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
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"Invalid CDisp scaling");
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}
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void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
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unsigned &physicalOperandIndex,
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unsigned numPhysicalOperands,
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const unsigned *operandMapping,
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OperandEncoding (*encodingFromString)
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(const std::string&,
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uint8_t OpSize)) {
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if (optional) {
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if (physicalOperandIndex >= numPhysicalOperands)
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return;
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} else {
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assert(physicalOperandIndex < numPhysicalOperands);
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}
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while (operandMapping[operandIndex] != operandIndex) {
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Spec->operands[operandIndex].encoding = ENCODING_DUP;
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Spec->operands[operandIndex].type =
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(OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
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++operandIndex;
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}
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StringRef typeName = (*Operands)[operandIndex].Rec->getName();
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OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize);
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// Adjust the encoding type for an operand based on the instruction.
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adjustOperandEncoding(encoding);
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Spec->operands[operandIndex].encoding = encoding;
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Spec->operands[operandIndex].type =
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typeFromString(std::string(typeName), HasREX_WPrefix, OpSize);
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++operandIndex;
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++physicalOperandIndex;
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}
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void RecognizableInstr::emitInstructionSpecifier() {
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Spec->name = Name;
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Spec->insnContext = insnContext();
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const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
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unsigned numOperands = OperandList.size();
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unsigned numPhysicalOperands = 0;
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// operandMapping maps from operands in OperandList to their originals.
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// If operandMapping[i] != i, then the entry is a duplicate.
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unsigned operandMapping[X86_MAX_OPERANDS];
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assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
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for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
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if (!OperandList[operandIndex].Constraints.empty()) {
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const CGIOperandList::ConstraintInfo &Constraint =
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OperandList[operandIndex].Constraints[0];
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if (Constraint.isTied()) {
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operandMapping[operandIndex] = operandIndex;
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operandMapping[Constraint.getTiedOperand()] = operandIndex;
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} else {
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++numPhysicalOperands;
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operandMapping[operandIndex] = operandIndex;
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}
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} else {
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++numPhysicalOperands;
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operandMapping[operandIndex] = operandIndex;
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}
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}
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#define HANDLE_OPERAND(class) \
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handleOperand(false, \
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operandIndex, \
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physicalOperandIndex, \
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|
numPhysicalOperands, \
|
|
operandMapping, \
|
|
class##EncodingFromString);
|
|
|
|
#define HANDLE_OPTIONAL(class) \
|
|
handleOperand(true, \
|
|
operandIndex, \
|
|
physicalOperandIndex, \
|
|
numPhysicalOperands, \
|
|
operandMapping, \
|
|
class##EncodingFromString);
|
|
|
|
// operandIndex should always be < numOperands
|
|
unsigned operandIndex = 0;
|
|
// physicalOperandIndex should always be < numPhysicalOperands
|
|
unsigned physicalOperandIndex = 0;
|
|
|
|
#ifndef NDEBUG
|
|
// Given the set of prefix bits, how many additional operands does the
|
|
// instruction have?
|
|
unsigned additionalOperands = 0;
|
|
if (HasVEX_4V)
|
|
++additionalOperands;
|
|
if (HasEVEX_K)
|
|
++additionalOperands;
|
|
#endif
|
|
|
|
switch (Form) {
|
|
default: llvm_unreachable("Unhandled form");
|
|
case X86Local::PrefixByte:
|
|
return;
|
|
case X86Local::RawFrmSrc:
|
|
HANDLE_OPERAND(relocation);
|
|
return;
|
|
case X86Local::RawFrmDst:
|
|
HANDLE_OPERAND(relocation);
|
|
return;
|
|
case X86Local::RawFrmDstSrc:
|
|
HANDLE_OPERAND(relocation);
|
|
HANDLE_OPERAND(relocation);
|
|
return;
|
|
case X86Local::RawFrm:
|
|
// Operand 1 (optional) is an address or immediate.
|
|
assert(numPhysicalOperands <= 1 &&
|
|
"Unexpected number of operands for RawFrm");
|
|
HANDLE_OPTIONAL(relocation)
|
|
break;
|
|
case X86Local::RawFrmMemOffs:
|
|
// Operand 1 is an address.
|
|
HANDLE_OPERAND(relocation);
|
|
break;
|
|
case X86Local::AddRegFrm:
|
|
// Operand 1 is added to the opcode.
|
|
// Operand 2 (optional) is an address.
|
|
assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
|
|
"Unexpected number of operands for AddRegFrm");
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
HANDLE_OPTIONAL(relocation)
|
|
break;
|
|
case X86Local::AddCCFrm:
|
|
// Operand 1 (optional) is an address or immediate.
|
|
assert(numPhysicalOperands == 2 &&
|
|
"Unexpected number of operands for AddCCFrm");
|
|
HANDLE_OPERAND(relocation)
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
break;
|
|
case X86Local::MRMDestReg:
|
|
// Operand 1 is a register operand in the R/M field.
|
|
// - In AVX512 there may be a mask operand here -
|
|
// Operand 2 is a register operand in the Reg/Opcode field.
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
|
// Operand 3 (optional) is an immediate.
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
numPhysicalOperands <= 3 + additionalOperands &&
|
|
"Unexpected number of operands for MRMDestRegFrm");
|
|
|
|
HANDLE_OPERAND(rmRegister)
|
|
if (HasEVEX_K)
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
if (HasVEX_4V)
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPTIONAL(immediate)
|
|
break;
|
|
case X86Local::MRMDestMem:
|
|
case X86Local::MRMDestMemFSIB:
|
|
// Operand 1 is a memory operand (possibly SIB-extended)
|
|
// Operand 2 is a register operand in the Reg/Opcode field.
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
|
// Operand 3 (optional) is an immediate.
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
numPhysicalOperands <= 3 + additionalOperands &&
|
|
"Unexpected number of operands for MRMDestMemFrm with VEX_4V");
|
|
|
|
HANDLE_OPERAND(memory)
|
|
|
|
if (HasEVEX_K)
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
if (HasVEX_4V)
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPTIONAL(immediate)
|
|
break;
|
|
case X86Local::MRMSrcReg:
|
|
// Operand 1 is a register operand in the Reg/Opcode field.
|
|
// Operand 2 is a register operand in the R/M field.
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
|
// Operand 3 (optional) is an immediate.
|
|
// Operand 4 (optional) is an immediate.
|
|
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
numPhysicalOperands <= 4 + additionalOperands &&
|
|
"Unexpected number of operands for MRMSrcRegFrm");
|
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
if (HasEVEX_K)
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
if (HasVEX_4V)
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
HANDLE_OPERAND(rmRegister)
|
|
HANDLE_OPTIONAL(immediate)
|
|
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
|
|
break;
|
|
case X86Local::MRMSrcReg4VOp3:
|
|
assert(numPhysicalOperands == 3 &&
|
|
"Unexpected number of operands for MRMSrcReg4VOp3Frm");
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPERAND(rmRegister)
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
break;
|
|
case X86Local::MRMSrcRegOp4:
|
|
assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
|
|
"Unexpected number of operands for MRMSrcRegOp4Frm");
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
HANDLE_OPERAND(immediate) // Register in imm[7:4]
|
|
HANDLE_OPERAND(rmRegister)
|
|
HANDLE_OPTIONAL(immediate)
|
|
break;
|
|
case X86Local::MRMSrcRegCC:
|
|
assert(numPhysicalOperands == 3 &&
|
|
"Unexpected number of operands for MRMSrcRegCC");
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPERAND(rmRegister)
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
break;
|
|
case X86Local::MRMSrcMem:
|
|
case X86Local::MRMSrcMemFSIB:
|
|
// Operand 1 is a register operand in the Reg/Opcode field.
|
|
// Operand 2 is a memory operand (possibly SIB-extended)
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
|
// Operand 3 (optional) is an immediate.
|
|
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
numPhysicalOperands <= 4 + additionalOperands &&
|
|
"Unexpected number of operands for MRMSrcMemFrm");
|
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
if (HasEVEX_K)
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
if (HasVEX_4V)
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
HANDLE_OPERAND(memory)
|
|
HANDLE_OPTIONAL(immediate)
|
|
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
|
|
break;
|
|
case X86Local::MRMSrcMem4VOp3:
|
|
assert(numPhysicalOperands == 3 &&
|
|
"Unexpected number of operands for MRMSrcMem4VOp3Frm");
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPERAND(memory)
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
break;
|
|
case X86Local::MRMSrcMemOp4:
|
|
assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
|
|
"Unexpected number of operands for MRMSrcMemOp4Frm");
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
HANDLE_OPERAND(immediate) // Register in imm[7:4]
|
|
HANDLE_OPERAND(memory)
|
|
HANDLE_OPTIONAL(immediate)
|
|
break;
|
|
case X86Local::MRMSrcMemCC:
|
|
assert(numPhysicalOperands == 3 &&
|
|
"Unexpected number of operands for MRMSrcMemCC");
|
|
HANDLE_OPERAND(roRegister)
|
|
HANDLE_OPERAND(memory)
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
break;
|
|
case X86Local::MRMXrCC:
|
|
assert(numPhysicalOperands == 2 &&
|
|
"Unexpected number of operands for MRMXrCC");
|
|
HANDLE_OPERAND(rmRegister)
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
break;
|
|
case X86Local::MRMr0:
|
|
// Operand 1 is a register operand in the R/M field.
|
|
HANDLE_OPERAND(roRegister)
|
|
break;
|
|
case X86Local::MRMXr:
|
|
case X86Local::MRM0r:
|
|
case X86Local::MRM1r:
|
|
case X86Local::MRM2r:
|
|
case X86Local::MRM3r:
|
|
case X86Local::MRM4r:
|
|
case X86Local::MRM5r:
|
|
case X86Local::MRM6r:
|
|
case X86Local::MRM7r:
|
|
// Operand 1 is a register operand in the R/M field.
|
|
// Operand 2 (optional) is an immediate or relocation.
|
|
// Operand 3 (optional) is an immediate.
|
|
assert(numPhysicalOperands >= 0 + additionalOperands &&
|
|
numPhysicalOperands <= 3 + additionalOperands &&
|
|
"Unexpected number of operands for MRMnr");
|
|
|
|
if (HasVEX_4V)
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
if (HasEVEX_K)
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
HANDLE_OPTIONAL(rmRegister)
|
|
HANDLE_OPTIONAL(relocation)
|
|
HANDLE_OPTIONAL(immediate)
|
|
break;
|
|
case X86Local::MRMXmCC:
|
|
assert(numPhysicalOperands == 2 &&
|
|
"Unexpected number of operands for MRMXm");
|
|
HANDLE_OPERAND(memory)
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
break;
|
|
case X86Local::MRMXm:
|
|
case X86Local::MRM0m:
|
|
case X86Local::MRM1m:
|
|
case X86Local::MRM2m:
|
|
case X86Local::MRM3m:
|
|
case X86Local::MRM4m:
|
|
case X86Local::MRM5m:
|
|
case X86Local::MRM6m:
|
|
case X86Local::MRM7m:
|
|
// Operand 1 is a memory operand (possibly SIB-extended)
|
|
// Operand 2 (optional) is an immediate or relocation.
|
|
assert(numPhysicalOperands >= 1 + additionalOperands &&
|
|
numPhysicalOperands <= 2 + additionalOperands &&
|
|
"Unexpected number of operands for MRMnm");
|
|
|
|
if (HasVEX_4V)
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
if (HasEVEX_K)
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
HANDLE_OPERAND(memory)
|
|
HANDLE_OPTIONAL(relocation)
|
|
break;
|
|
case X86Local::RawFrmImm8:
|
|
// operand 1 is a 16-bit immediate
|
|
// operand 2 is an 8-bit immediate
|
|
assert(numPhysicalOperands == 2 &&
|
|
"Unexpected number of operands for X86Local::RawFrmImm8");
|
|
HANDLE_OPERAND(immediate)
|
|
HANDLE_OPERAND(immediate)
|
|
break;
|
|
case X86Local::RawFrmImm16:
|
|
// operand 1 is a 16-bit immediate
|
|
// operand 2 is a 16-bit immediate
|
|
HANDLE_OPERAND(immediate)
|
|
HANDLE_OPERAND(immediate)
|
|
break;
|
|
case X86Local::MRM0X:
|
|
case X86Local::MRM1X:
|
|
case X86Local::MRM2X:
|
|
case X86Local::MRM3X:
|
|
case X86Local::MRM4X:
|
|
case X86Local::MRM5X:
|
|
case X86Local::MRM6X:
|
|
case X86Local::MRM7X:
|
|
#define MAP(from, to) case X86Local::MRM_##from:
|
|
X86_INSTR_MRM_MAPPING
|
|
#undef MAP
|
|
HANDLE_OPTIONAL(relocation)
|
|
break;
|
|
}
|
|
|
|
#undef HANDLE_OPERAND
|
|
#undef HANDLE_OPTIONAL
|
|
}
|
|
|
|
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
|
|
// Special cases where the LLVM tables are not complete
|
|
|
|
#define MAP(from, to) \
|
|
case X86Local::MRM_##from:
|
|
|
|
llvm::Optional<OpcodeType> opcodeType;
|
|
switch (OpMap) {
|
|
default: llvm_unreachable("Invalid map!");
|
|
case X86Local::OB: opcodeType = ONEBYTE; break;
|
|
case X86Local::TB: opcodeType = TWOBYTE; break;
|
|
case X86Local::T8: opcodeType = THREEBYTE_38; break;
|
|
case X86Local::TA: opcodeType = THREEBYTE_3A; break;
|
|
case X86Local::XOP8: opcodeType = XOP8_MAP; break;
|
|
case X86Local::XOP9: opcodeType = XOP9_MAP; break;
|
|
case X86Local::XOPA: opcodeType = XOPA_MAP; break;
|
|
case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
|
|
case X86Local::T_MAP5: opcodeType = MAP5; break;
|
|
case X86Local::T_MAP6: opcodeType = MAP6; break;
|
|
}
|
|
|
|
std::unique_ptr<ModRMFilter> filter;
|
|
switch (Form) {
|
|
default: llvm_unreachable("Invalid form!");
|
|
case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
|
|
case X86Local::RawFrm:
|
|
case X86Local::AddRegFrm:
|
|
case X86Local::RawFrmMemOffs:
|
|
case X86Local::RawFrmSrc:
|
|
case X86Local::RawFrmDst:
|
|
case X86Local::RawFrmDstSrc:
|
|
case X86Local::RawFrmImm8:
|
|
case X86Local::RawFrmImm16:
|
|
case X86Local::AddCCFrm:
|
|
case X86Local::PrefixByte:
|
|
filter = std::make_unique<DumbFilter>();
|
|
break;
|
|
case X86Local::MRMDestReg:
|
|
case X86Local::MRMSrcReg:
|
|
case X86Local::MRMSrcReg4VOp3:
|
|
case X86Local::MRMSrcRegOp4:
|
|
case X86Local::MRMSrcRegCC:
|
|
case X86Local::MRMXrCC:
|
|
case X86Local::MRMXr:
|
|
filter = std::make_unique<ModFilter>(true);
|
|
break;
|
|
case X86Local::MRMDestMem:
|
|
case X86Local::MRMDestMemFSIB:
|
|
case X86Local::MRMSrcMem:
|
|
case X86Local::MRMSrcMemFSIB:
|
|
case X86Local::MRMSrcMem4VOp3:
|
|
case X86Local::MRMSrcMemOp4:
|
|
case X86Local::MRMSrcMemCC:
|
|
case X86Local::MRMXmCC:
|
|
case X86Local::MRMXm:
|
|
filter = std::make_unique<ModFilter>(false);
|
|
break;
|
|
case X86Local::MRM0r: case X86Local::MRM1r:
|
|
case X86Local::MRM2r: case X86Local::MRM3r:
|
|
case X86Local::MRM4r: case X86Local::MRM5r:
|
|
case X86Local::MRM6r: case X86Local::MRM7r:
|
|
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
|
|
break;
|
|
case X86Local::MRM0X: case X86Local::MRM1X:
|
|
case X86Local::MRM2X: case X86Local::MRM3X:
|
|
case X86Local::MRM4X: case X86Local::MRM5X:
|
|
case X86Local::MRM6X: case X86Local::MRM7X:
|
|
filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
|
|
break;
|
|
case X86Local::MRMr0:
|
|
filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
|
|
break;
|
|
case X86Local::MRM0m: case X86Local::MRM1m:
|
|
case X86Local::MRM2m: case X86Local::MRM3m:
|
|
case X86Local::MRM4m: case X86Local::MRM5m:
|
|
case X86Local::MRM6m: case X86Local::MRM7m:
|
|
filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
|
|
break;
|
|
X86_INSTR_MRM_MAPPING
|
|
filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
|
|
break;
|
|
} // switch (Form)
|
|
|
|
uint8_t opcodeToSet = Opcode;
|
|
|
|
unsigned AddressSize = 0;
|
|
switch (AdSize) {
|
|
case X86Local::AdSize16: AddressSize = 16; break;
|
|
case X86Local::AdSize32: AddressSize = 32; break;
|
|
case X86Local::AdSize64: AddressSize = 64; break;
|
|
}
|
|
|
|
assert(opcodeType && "Opcode type not set");
|
|
assert(filter && "Filter not set");
|
|
|
|
if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
|
|
Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
|
|
Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) {
|
|
unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16;
|
|
assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
|
|
|
|
uint8_t currentOpcode;
|
|
|
|
for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + Count;
|
|
++currentOpcode)
|
|
tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
|
|
UID, Is32Bit, OpPrefix == 0,
|
|
IgnoresVEX_L || EncodeRC,
|
|
IgnoresVEX_W, AddressSize);
|
|
} else {
|
|
tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
|
|
Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
|
|
IgnoresVEX_W, AddressSize);
|
|
}
|
|
|
|
#undef MAP
|
|
}
|
|
|
|
#define TYPE(str, type) if (s == str) return type;
|
|
OperandType RecognizableInstr::typeFromString(const std::string &s,
|
|
bool hasREX_WPrefix,
|
|
uint8_t OpSize) {
|
|
if(hasREX_WPrefix) {
|
|
// For instructions with a REX_W prefix, a declared 32-bit register encoding
|
|
// is special.
|
|
TYPE("GR32", TYPE_R32)
|
|
}
|
|
if(OpSize == X86Local::OpSize16) {
|
|
// For OpSize16 instructions, a declared 16-bit register or
|
|
// immediate encoding is special.
|
|
TYPE("GR16", TYPE_Rv)
|
|
} else if(OpSize == X86Local::OpSize32) {
|
|
// For OpSize32 instructions, a declared 32-bit register or
|
|
// immediate encoding is special.
|
|
TYPE("GR32", TYPE_Rv)
|
|
}
|
|
TYPE("i16mem", TYPE_M)
|
|
TYPE("i16imm", TYPE_IMM)
|
|
TYPE("i16i8imm", TYPE_IMM)
|
|
TYPE("GR16", TYPE_R16)
|
|
TYPE("GR16orGR32orGR64", TYPE_R16)
|
|
TYPE("i32mem", TYPE_M)
|
|
TYPE("i32imm", TYPE_IMM)
|
|
TYPE("i32i8imm", TYPE_IMM)
|
|
TYPE("GR32", TYPE_R32)
|
|
TYPE("GR32orGR64", TYPE_R32)
|
|
TYPE("i64mem", TYPE_M)
|
|
TYPE("i64i32imm", TYPE_IMM)
|
|
TYPE("i64i8imm", TYPE_IMM)
|
|
TYPE("GR64", TYPE_R64)
|
|
TYPE("i8mem", TYPE_M)
|
|
TYPE("i8imm", TYPE_IMM)
|
|
TYPE("u4imm", TYPE_UIMM8)
|
|
TYPE("u8imm", TYPE_UIMM8)
|
|
TYPE("i16u8imm", TYPE_UIMM8)
|
|
TYPE("i32u8imm", TYPE_UIMM8)
|
|
TYPE("i64u8imm", TYPE_UIMM8)
|
|
TYPE("GR8", TYPE_R8)
|
|
TYPE("VR128", TYPE_XMM)
|
|
TYPE("VR128X", TYPE_XMM)
|
|
TYPE("f128mem", TYPE_M)
|
|
TYPE("f256mem", TYPE_M)
|
|
TYPE("f512mem", TYPE_M)
|
|
TYPE("FR128", TYPE_XMM)
|
|
TYPE("FR64", TYPE_XMM)
|
|
TYPE("FR64X", TYPE_XMM)
|
|
TYPE("f64mem", TYPE_M)
|
|
TYPE("sdmem", TYPE_M)
|
|
TYPE("FR16X", TYPE_XMM)
|
|
TYPE("FR32", TYPE_XMM)
|
|
TYPE("FR32X", TYPE_XMM)
|
|
TYPE("f32mem", TYPE_M)
|
|
TYPE("f16mem", TYPE_M)
|
|
TYPE("ssmem", TYPE_M)
|
|
TYPE("shmem", TYPE_M)
|
|
TYPE("RST", TYPE_ST)
|
|
TYPE("RSTi", TYPE_ST)
|
|
TYPE("i128mem", TYPE_M)
|
|
TYPE("i256mem", TYPE_M)
|
|
TYPE("i512mem", TYPE_M)
|
|
TYPE("i64i32imm_brtarget", TYPE_REL)
|
|
TYPE("i16imm_brtarget", TYPE_REL)
|
|
TYPE("i32imm_brtarget", TYPE_REL)
|
|
TYPE("ccode", TYPE_IMM)
|
|
TYPE("AVX512RC", TYPE_IMM)
|
|
TYPE("brtarget32", TYPE_REL)
|
|
TYPE("brtarget16", TYPE_REL)
|
|
TYPE("brtarget8", TYPE_REL)
|
|
TYPE("f80mem", TYPE_M)
|
|
TYPE("lea64_32mem", TYPE_M)
|
|
TYPE("lea64mem", TYPE_M)
|
|
TYPE("VR64", TYPE_MM64)
|
|
TYPE("i64imm", TYPE_IMM)
|
|
TYPE("anymem", TYPE_M)
|
|
TYPE("opaquemem", TYPE_M)
|
|
TYPE("sibmem", TYPE_MSIB)
|
|
TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
|
|
TYPE("DEBUG_REG", TYPE_DEBUGREG)
|
|
TYPE("CONTROL_REG", TYPE_CONTROLREG)
|
|
TYPE("srcidx8", TYPE_SRCIDX)
|
|
TYPE("srcidx16", TYPE_SRCIDX)
|
|
TYPE("srcidx32", TYPE_SRCIDX)
|
|
TYPE("srcidx64", TYPE_SRCIDX)
|
|
TYPE("dstidx8", TYPE_DSTIDX)
|
|
TYPE("dstidx16", TYPE_DSTIDX)
|
|
TYPE("dstidx32", TYPE_DSTIDX)
|
|
TYPE("dstidx64", TYPE_DSTIDX)
|
|
TYPE("offset16_8", TYPE_MOFFS)
|
|
TYPE("offset16_16", TYPE_MOFFS)
|
|
TYPE("offset16_32", TYPE_MOFFS)
|
|
TYPE("offset32_8", TYPE_MOFFS)
|
|
TYPE("offset32_16", TYPE_MOFFS)
|
|
TYPE("offset32_32", TYPE_MOFFS)
|
|
TYPE("offset32_64", TYPE_MOFFS)
|
|
TYPE("offset64_8", TYPE_MOFFS)
|
|
TYPE("offset64_16", TYPE_MOFFS)
|
|
TYPE("offset64_32", TYPE_MOFFS)
|
|
TYPE("offset64_64", TYPE_MOFFS)
|
|
TYPE("VR256", TYPE_YMM)
|
|
TYPE("VR256X", TYPE_YMM)
|
|
TYPE("VR512", TYPE_ZMM)
|
|
TYPE("VK1", TYPE_VK)
|
|
TYPE("VK1WM", TYPE_VK)
|
|
TYPE("VK2", TYPE_VK)
|
|
TYPE("VK2WM", TYPE_VK)
|
|
TYPE("VK4", TYPE_VK)
|
|
TYPE("VK4WM", TYPE_VK)
|
|
TYPE("VK8", TYPE_VK)
|
|
TYPE("VK8WM", TYPE_VK)
|
|
TYPE("VK16", TYPE_VK)
|
|
TYPE("VK16WM", TYPE_VK)
|
|
TYPE("VK32", TYPE_VK)
|
|
TYPE("VK32WM", TYPE_VK)
|
|
TYPE("VK64", TYPE_VK)
|
|
TYPE("VK64WM", TYPE_VK)
|
|
TYPE("VK1Pair", TYPE_VK_PAIR)
|
|
TYPE("VK2Pair", TYPE_VK_PAIR)
|
|
TYPE("VK4Pair", TYPE_VK_PAIR)
|
|
TYPE("VK8Pair", TYPE_VK_PAIR)
|
|
TYPE("VK16Pair", TYPE_VK_PAIR)
|
|
TYPE("vx64mem", TYPE_MVSIBX)
|
|
TYPE("vx128mem", TYPE_MVSIBX)
|
|
TYPE("vx256mem", TYPE_MVSIBX)
|
|
TYPE("vy128mem", TYPE_MVSIBY)
|
|
TYPE("vy256mem", TYPE_MVSIBY)
|
|
TYPE("vx64xmem", TYPE_MVSIBX)
|
|
TYPE("vx128xmem", TYPE_MVSIBX)
|
|
TYPE("vx256xmem", TYPE_MVSIBX)
|
|
TYPE("vy128xmem", TYPE_MVSIBY)
|
|
TYPE("vy256xmem", TYPE_MVSIBY)
|
|
TYPE("vy512xmem", TYPE_MVSIBY)
|
|
TYPE("vz256mem", TYPE_MVSIBZ)
|
|
TYPE("vz512mem", TYPE_MVSIBZ)
|
|
TYPE("BNDR", TYPE_BNDR)
|
|
TYPE("TILE", TYPE_TMM)
|
|
errs() << "Unhandled type string " << s << "\n";
|
|
llvm_unreachable("Unhandled type string");
|
|
}
|
|
#undef TYPE
|
|
|
|
#define ENCODING(str, encoding) if (s == str) return encoding;
|
|
OperandEncoding
|
|
RecognizableInstr::immediateEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
if(OpSize != X86Local::OpSize16) {
|
|
// For instructions without an OpSize prefix, a declared 16-bit register or
|
|
// immediate encoding is special.
|
|
ENCODING("i16imm", ENCODING_IW)
|
|
}
|
|
ENCODING("i32i8imm", ENCODING_IB)
|
|
ENCODING("AVX512RC", ENCODING_IRC)
|
|
ENCODING("i16imm", ENCODING_Iv)
|
|
ENCODING("i16i8imm", ENCODING_IB)
|
|
ENCODING("i32imm", ENCODING_Iv)
|
|
ENCODING("i64i32imm", ENCODING_ID)
|
|
ENCODING("i64i8imm", ENCODING_IB)
|
|
ENCODING("i8imm", ENCODING_IB)
|
|
ENCODING("u4imm", ENCODING_IB)
|
|
ENCODING("u8imm", ENCODING_IB)
|
|
ENCODING("i16u8imm", ENCODING_IB)
|
|
ENCODING("i32u8imm", ENCODING_IB)
|
|
ENCODING("i64u8imm", ENCODING_IB)
|
|
// This is not a typo. Instructions like BLENDVPD put
|
|
// register IDs in 8-bit immediates nowadays.
|
|
ENCODING("FR32", ENCODING_IB)
|
|
ENCODING("FR64", ENCODING_IB)
|
|
ENCODING("FR128", ENCODING_IB)
|
|
ENCODING("VR128", ENCODING_IB)
|
|
ENCODING("VR256", ENCODING_IB)
|
|
ENCODING("FR16X", ENCODING_IB)
|
|
ENCODING("FR32X", ENCODING_IB)
|
|
ENCODING("FR64X", ENCODING_IB)
|
|
ENCODING("VR128X", ENCODING_IB)
|
|
ENCODING("VR256X", ENCODING_IB)
|
|
ENCODING("VR512", ENCODING_IB)
|
|
ENCODING("TILE", ENCODING_IB)
|
|
errs() << "Unhandled immediate encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled immediate encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
ENCODING("RST", ENCODING_FP)
|
|
ENCODING("RSTi", ENCODING_FP)
|
|
ENCODING("GR16", ENCODING_RM)
|
|
ENCODING("GR16orGR32orGR64",ENCODING_RM)
|
|
ENCODING("GR32", ENCODING_RM)
|
|
ENCODING("GR32orGR64", ENCODING_RM)
|
|
ENCODING("GR64", ENCODING_RM)
|
|
ENCODING("GR8", ENCODING_RM)
|
|
ENCODING("VR128", ENCODING_RM)
|
|
ENCODING("VR128X", ENCODING_RM)
|
|
ENCODING("FR128", ENCODING_RM)
|
|
ENCODING("FR64", ENCODING_RM)
|
|
ENCODING("FR32", ENCODING_RM)
|
|
ENCODING("FR64X", ENCODING_RM)
|
|
ENCODING("FR32X", ENCODING_RM)
|
|
ENCODING("FR16X", ENCODING_RM)
|
|
ENCODING("VR64", ENCODING_RM)
|
|
ENCODING("VR256", ENCODING_RM)
|
|
ENCODING("VR256X", ENCODING_RM)
|
|
ENCODING("VR512", ENCODING_RM)
|
|
ENCODING("VK1", ENCODING_RM)
|
|
ENCODING("VK2", ENCODING_RM)
|
|
ENCODING("VK4", ENCODING_RM)
|
|
ENCODING("VK8", ENCODING_RM)
|
|
ENCODING("VK16", ENCODING_RM)
|
|
ENCODING("VK32", ENCODING_RM)
|
|
ENCODING("VK64", ENCODING_RM)
|
|
ENCODING("BNDR", ENCODING_RM)
|
|
ENCODING("TILE", ENCODING_RM)
|
|
errs() << "Unhandled R/M register encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled R/M register encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
ENCODING("GR16", ENCODING_REG)
|
|
ENCODING("GR16orGR32orGR64",ENCODING_REG)
|
|
ENCODING("GR32", ENCODING_REG)
|
|
ENCODING("GR32orGR64", ENCODING_REG)
|
|
ENCODING("GR64", ENCODING_REG)
|
|
ENCODING("GR8", ENCODING_REG)
|
|
ENCODING("VR128", ENCODING_REG)
|
|
ENCODING("FR128", ENCODING_REG)
|
|
ENCODING("FR64", ENCODING_REG)
|
|
ENCODING("FR32", ENCODING_REG)
|
|
ENCODING("VR64", ENCODING_REG)
|
|
ENCODING("SEGMENT_REG", ENCODING_REG)
|
|
ENCODING("DEBUG_REG", ENCODING_REG)
|
|
ENCODING("CONTROL_REG", ENCODING_REG)
|
|
ENCODING("VR256", ENCODING_REG)
|
|
ENCODING("VR256X", ENCODING_REG)
|
|
ENCODING("VR128X", ENCODING_REG)
|
|
ENCODING("FR64X", ENCODING_REG)
|
|
ENCODING("FR32X", ENCODING_REG)
|
|
ENCODING("FR16X", ENCODING_REG)
|
|
ENCODING("VR512", ENCODING_REG)
|
|
ENCODING("VK1", ENCODING_REG)
|
|
ENCODING("VK2", ENCODING_REG)
|
|
ENCODING("VK4", ENCODING_REG)
|
|
ENCODING("VK8", ENCODING_REG)
|
|
ENCODING("VK16", ENCODING_REG)
|
|
ENCODING("VK32", ENCODING_REG)
|
|
ENCODING("VK64", ENCODING_REG)
|
|
ENCODING("VK1Pair", ENCODING_REG)
|
|
ENCODING("VK2Pair", ENCODING_REG)
|
|
ENCODING("VK4Pair", ENCODING_REG)
|
|
ENCODING("VK8Pair", ENCODING_REG)
|
|
ENCODING("VK16Pair", ENCODING_REG)
|
|
ENCODING("VK1WM", ENCODING_REG)
|
|
ENCODING("VK2WM", ENCODING_REG)
|
|
ENCODING("VK4WM", ENCODING_REG)
|
|
ENCODING("VK8WM", ENCODING_REG)
|
|
ENCODING("VK16WM", ENCODING_REG)
|
|
ENCODING("VK32WM", ENCODING_REG)
|
|
ENCODING("VK64WM", ENCODING_REG)
|
|
ENCODING("BNDR", ENCODING_REG)
|
|
ENCODING("TILE", ENCODING_REG)
|
|
errs() << "Unhandled reg/opcode register encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled reg/opcode register encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
ENCODING("GR32", ENCODING_VVVV)
|
|
ENCODING("GR64", ENCODING_VVVV)
|
|
ENCODING("FR32", ENCODING_VVVV)
|
|
ENCODING("FR128", ENCODING_VVVV)
|
|
ENCODING("FR64", ENCODING_VVVV)
|
|
ENCODING("VR128", ENCODING_VVVV)
|
|
ENCODING("VR256", ENCODING_VVVV)
|
|
ENCODING("FR16X", ENCODING_VVVV)
|
|
ENCODING("FR32X", ENCODING_VVVV)
|
|
ENCODING("FR64X", ENCODING_VVVV)
|
|
ENCODING("VR128X", ENCODING_VVVV)
|
|
ENCODING("VR256X", ENCODING_VVVV)
|
|
ENCODING("VR512", ENCODING_VVVV)
|
|
ENCODING("VK1", ENCODING_VVVV)
|
|
ENCODING("VK2", ENCODING_VVVV)
|
|
ENCODING("VK4", ENCODING_VVVV)
|
|
ENCODING("VK8", ENCODING_VVVV)
|
|
ENCODING("VK16", ENCODING_VVVV)
|
|
ENCODING("VK32", ENCODING_VVVV)
|
|
ENCODING("VK64", ENCODING_VVVV)
|
|
ENCODING("TILE", ENCODING_VVVV)
|
|
errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled VEX.vvvv register encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
ENCODING("VK1WM", ENCODING_WRITEMASK)
|
|
ENCODING("VK2WM", ENCODING_WRITEMASK)
|
|
ENCODING("VK4WM", ENCODING_WRITEMASK)
|
|
ENCODING("VK8WM", ENCODING_WRITEMASK)
|
|
ENCODING("VK16WM", ENCODING_WRITEMASK)
|
|
ENCODING("VK32WM", ENCODING_WRITEMASK)
|
|
ENCODING("VK64WM", ENCODING_WRITEMASK)
|
|
errs() << "Unhandled mask register encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled mask register encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::memoryEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
ENCODING("i16mem", ENCODING_RM)
|
|
ENCODING("i32mem", ENCODING_RM)
|
|
ENCODING("i64mem", ENCODING_RM)
|
|
ENCODING("i8mem", ENCODING_RM)
|
|
ENCODING("shmem", ENCODING_RM)
|
|
ENCODING("ssmem", ENCODING_RM)
|
|
ENCODING("sdmem", ENCODING_RM)
|
|
ENCODING("f128mem", ENCODING_RM)
|
|
ENCODING("f256mem", ENCODING_RM)
|
|
ENCODING("f512mem", ENCODING_RM)
|
|
ENCODING("f64mem", ENCODING_RM)
|
|
ENCODING("f32mem", ENCODING_RM)
|
|
ENCODING("f16mem", ENCODING_RM)
|
|
ENCODING("i128mem", ENCODING_RM)
|
|
ENCODING("i256mem", ENCODING_RM)
|
|
ENCODING("i512mem", ENCODING_RM)
|
|
ENCODING("f80mem", ENCODING_RM)
|
|
ENCODING("lea64_32mem", ENCODING_RM)
|
|
ENCODING("lea64mem", ENCODING_RM)
|
|
ENCODING("anymem", ENCODING_RM)
|
|
ENCODING("opaquemem", ENCODING_RM)
|
|
ENCODING("sibmem", ENCODING_SIB)
|
|
ENCODING("vx64mem", ENCODING_VSIB)
|
|
ENCODING("vx128mem", ENCODING_VSIB)
|
|
ENCODING("vx256mem", ENCODING_VSIB)
|
|
ENCODING("vy128mem", ENCODING_VSIB)
|
|
ENCODING("vy256mem", ENCODING_VSIB)
|
|
ENCODING("vx64xmem", ENCODING_VSIB)
|
|
ENCODING("vx128xmem", ENCODING_VSIB)
|
|
ENCODING("vx256xmem", ENCODING_VSIB)
|
|
ENCODING("vy128xmem", ENCODING_VSIB)
|
|
ENCODING("vy256xmem", ENCODING_VSIB)
|
|
ENCODING("vy512xmem", ENCODING_VSIB)
|
|
ENCODING("vz256mem", ENCODING_VSIB)
|
|
ENCODING("vz512mem", ENCODING_VSIB)
|
|
errs() << "Unhandled memory encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled memory encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::relocationEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
if(OpSize != X86Local::OpSize16) {
|
|
// For instructions without an OpSize prefix, a declared 16-bit register or
|
|
// immediate encoding is special.
|
|
ENCODING("i16imm", ENCODING_IW)
|
|
}
|
|
ENCODING("i16imm", ENCODING_Iv)
|
|
ENCODING("i16i8imm", ENCODING_IB)
|
|
ENCODING("i32imm", ENCODING_Iv)
|
|
ENCODING("i32i8imm", ENCODING_IB)
|
|
ENCODING("i64i32imm", ENCODING_ID)
|
|
ENCODING("i64i8imm", ENCODING_IB)
|
|
ENCODING("i8imm", ENCODING_IB)
|
|
ENCODING("u8imm", ENCODING_IB)
|
|
ENCODING("i16u8imm", ENCODING_IB)
|
|
ENCODING("i32u8imm", ENCODING_IB)
|
|
ENCODING("i64u8imm", ENCODING_IB)
|
|
ENCODING("i64i32imm_brtarget", ENCODING_ID)
|
|
ENCODING("i16imm_brtarget", ENCODING_IW)
|
|
ENCODING("i32imm_brtarget", ENCODING_ID)
|
|
ENCODING("brtarget32", ENCODING_ID)
|
|
ENCODING("brtarget16", ENCODING_IW)
|
|
ENCODING("brtarget8", ENCODING_IB)
|
|
ENCODING("i64imm", ENCODING_IO)
|
|
ENCODING("offset16_8", ENCODING_Ia)
|
|
ENCODING("offset16_16", ENCODING_Ia)
|
|
ENCODING("offset16_32", ENCODING_Ia)
|
|
ENCODING("offset32_8", ENCODING_Ia)
|
|
ENCODING("offset32_16", ENCODING_Ia)
|
|
ENCODING("offset32_32", ENCODING_Ia)
|
|
ENCODING("offset32_64", ENCODING_Ia)
|
|
ENCODING("offset64_8", ENCODING_Ia)
|
|
ENCODING("offset64_16", ENCODING_Ia)
|
|
ENCODING("offset64_32", ENCODING_Ia)
|
|
ENCODING("offset64_64", ENCODING_Ia)
|
|
ENCODING("srcidx8", ENCODING_SI)
|
|
ENCODING("srcidx16", ENCODING_SI)
|
|
ENCODING("srcidx32", ENCODING_SI)
|
|
ENCODING("srcidx64", ENCODING_SI)
|
|
ENCODING("dstidx8", ENCODING_DI)
|
|
ENCODING("dstidx16", ENCODING_DI)
|
|
ENCODING("dstidx32", ENCODING_DI)
|
|
ENCODING("dstidx64", ENCODING_DI)
|
|
errs() << "Unhandled relocation encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled relocation encoding");
|
|
}
|
|
|
|
OperandEncoding
|
|
RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
|
|
uint8_t OpSize) {
|
|
ENCODING("GR32", ENCODING_Rv)
|
|
ENCODING("GR64", ENCODING_RO)
|
|
ENCODING("GR16", ENCODING_Rv)
|
|
ENCODING("GR8", ENCODING_RB)
|
|
ENCODING("ccode", ENCODING_CC)
|
|
errs() << "Unhandled opcode modifier encoding " << s << "\n";
|
|
llvm_unreachable("Unhandled opcode modifier encoding");
|
|
}
|
|
#undef ENCODING
|