145 lines
5.9 KiB
C++
145 lines
5.9 KiB
C++
//===---- MipsISelDAGToDAG.h - A Dag to Dag Inst Selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
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#define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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class MipsDAGToDAGISel : public SelectionDAGISel {
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
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: SelectionDAGISel(TM, OL), Subtarget(nullptr) {}
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// Pass Name
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StringRef getPassName() const override {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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protected:
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SDNode *getGlobalBaseReg();
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/// Keep a pointer to the MipsSubtarget around so that we can make the right
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/// decision when generating code for different targets.
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const MipsSubtarget *Subtarget;
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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// Complex Pattern.
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/// (reg + imm).
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virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Fall back on this function if all else fails.
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virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Match integer address pattern.
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virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddr16MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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/// Match addr+simm10 and addr
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virtual bool selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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virtual bool selectAddr16(SDValue Addr, SDValue &Base, SDValue &Offset);
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virtual bool selectAddr16SP(SDValue Addr, SDValue &Base, SDValue &Offset);
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/// \brief Select constant vector splats.
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virtual bool selectVSplat(SDNode *N, APInt &Imm,
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unsigned MinSizeInBits) const;
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/// \brief Select constant vector splats whose value fits in a uimm1.
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virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm2.
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virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm3.
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virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm4.
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virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm5.
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virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm6.
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virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a uimm8.
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virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value fits in a simm5.
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virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is a power of 2.
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virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is the inverse of a
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/// power of 2.
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virtual bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is a run of set bits
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/// ending at the most significant bit
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virtual bool selectVSplatMaskL(SDValue N, SDValue &Imm) const;
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/// \brief Select constant vector splats whose value is a run of set bits
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/// starting at bit zero.
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virtual bool selectVSplatMaskR(SDValue N, SDValue &Imm) const;
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void Select(SDNode *N) override;
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virtual bool trySelect(SDNode *Node) = 0;
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// getImm - Return a target constant with the specified value.
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inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0));
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}
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virtual void processFunctionAfterISel(MachineFunction &MF) = 0;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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};
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}
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#endif
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