665 lines
25 KiB
C++
665 lines
25 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using are sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Config/alloca.h"
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#include <algorithm>
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using namespace llvm;
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char LiveVariables::ID = 0;
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static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
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void LiveVariables::VarInfo::dump() const {
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cerr << " Alive in blocks: ";
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for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
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if (AliveBlocks[i]) cerr << i << ", ";
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cerr << " Used in blocks: ";
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for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
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if (UsedBlocks[i]) cerr << i << ", ";
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cerr << "\n Killed by:";
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if (Kills.empty())
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cerr << " No instructions.\n";
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else {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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cerr << "\n #" << i << ": " << *Kills[i];
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cerr << "\n";
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}
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}
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/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
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LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
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assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
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"getVarInfo: not a virtual register!");
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RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
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if (RegIdx >= VirtRegInfo.size()) {
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if (RegIdx >= 2*VirtRegInfo.size())
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VirtRegInfo.resize(RegIdx*2);
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else
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VirtRegInfo.resize(2*VirtRegInfo.size());
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}
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VarInfo &VI = VirtRegInfo[RegIdx];
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VI.AliveBlocks.resize(MF->getNumBlockIDs());
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VI.UsedBlocks.resize(MF->getNumBlockIDs());
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return VI;
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}
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/// KillsRegister - Returns true if the machine instruction kills the specified
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/// register.
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bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isKill()) {
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unsigned MOReg = MO.getReg();
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if (MOReg == Reg ||
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(TargetRegisterInfo::isPhysicalRegister(MOReg) &&
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TargetRegisterInfo::isPhysicalRegister(Reg) &&
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RegInfo->isSubRegister(MOReg, Reg)))
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return true;
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}
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}
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return false;
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}
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/// RegisterDefIsDead - Returns true if the register is dead in this machine
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/// instruction.
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bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDead()) {
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unsigned MOReg = MO.getReg();
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if ((MOReg == Reg) ||
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(TargetRegisterInfo::isPhysicalRegister(MOReg) &&
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TargetRegisterInfo::isPhysicalRegister(Reg) &&
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RegInfo->isSubRegister(MOReg, Reg)))
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return true;
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}
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}
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return false;
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}
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/// ModifiesRegister - Returns true if the machine instruction modifies the
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/// register.
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bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
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return true;
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}
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return false;
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
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MachineBasicBlock *DefBlock,
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MachineBasicBlock *MBB,
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std::vector<MachineBasicBlock*> &WorkList) {
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unsigned BBNum = MBB->getNumber();
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it.
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i]->getParent() == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == DefBlock) return; // Terminate recursion
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if (VRInfo.AliveBlocks[BBNum])
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks[BBNum] = true;
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for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
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E = MBB->pred_rend(); PI != E; ++PI)
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WorkList.push_back(*PI);
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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MachineBasicBlock *DefBlock,
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MachineBasicBlock *MBB) {
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std::vector<MachineBasicBlock*> WorkList;
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
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while (!WorkList.empty()) {
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MachineBasicBlock *Pred = WorkList.back();
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WorkList.pop_back();
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
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}
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}
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void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
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MachineInstr *MI) {
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const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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assert(MRI.getVRegDef(reg) && "Register use before def!");
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unsigned BBNum = MBB->getNumber();
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VarInfo& VRInfo = getVarInfo(reg);
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VRInfo.UsedBlocks[BBNum] = true;
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VRInfo.NumUses++;
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// Check to see if this basic block is already a kill block.
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back() = MI;
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return;
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}
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#ifndef NDEBUG
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
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#endif
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assert(MBB != MRI.getVRegDef(reg)->getParent() &&
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"Should have kill for defblock!");
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// Add a new kill entry for this basic block. If this virtual register is
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// already marked as alive in this basic block, that means it is alive in at
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// least one of the successor blocks, it's not a kill.
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if (!VRInfo.AliveBlocks[BBNum])
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VRInfo.Kills.push_back(MI);
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// Update all dominating blocks to mark them as "known live".
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for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
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}
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/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
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/// implicit defs to a machine instruction if there was an earlier def of its
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/// super-register.
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void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
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// Turn previous partial def's into read/mod/write.
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for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
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MachineInstr *Def = PhysRegPartDef[Reg][i];
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// First one is just a def. This means the use is reading some undef bits.
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if (i != 0)
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Def->addOperand(MachineOperand::CreateReg(Reg,
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false /*IsDef*/,
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true /*IsImp*/,
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true /*IsKill*/));
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Def->addOperand(MachineOperand::CreateReg(Reg,
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true /*IsDef*/,
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true /*IsImp*/));
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}
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PhysRegPartDef[Reg].clear();
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// There was an earlier def of a super-register. Add implicit def to that MI.
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//
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// A: EAX = ...
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// B: ... = AX
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//
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// Add implicit def to A.
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if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
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!PhysRegUsed[Reg]) {
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MachineInstr *Def = PhysRegInfo[Reg];
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if (!Def->findRegisterDefOperand(Reg))
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Def->addOperand(MachineOperand::CreateReg(Reg,
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true /*IsDef*/,
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true /*IsImp*/));
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}
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// There is a now a proper use, forget about the last partial use.
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PhysRegPartUse[Reg] = NULL;
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = true;
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// Now reset the use information for the sub-registers.
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegPartUse[SubReg] = NULL;
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PhysRegInfo[SubReg] = MI;
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PhysRegUsed[SubReg] = true;
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}
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs) {
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// Remember the partial use of this super-register if it was previously
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// defined.
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bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
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if (!HasPrevDef)
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// No need to go up more levels. A def of a register also sets its sub-
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// registers. So if PhysRegInfo[SuperReg] is NULL, it means SuperReg's
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// super-registers are not previously defined.
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for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
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unsigned SSReg = *SSRegs; ++SSRegs)
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if (PhysRegInfo[SSReg] != NULL) {
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HasPrevDef = true;
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break;
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}
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if (HasPrevDef) {
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PhysRegInfo[SuperReg] = MI;
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PhysRegPartUse[SuperReg] = MI;
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}
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}
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}
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/// addRegisterKills - For all of a register's sub-registers that are killed in
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/// at this machine instruction, mark them as "killed". (If the machine operand
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/// isn't found, add it first.)
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void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
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SmallSet<unsigned, 4> &SubKills) {
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if (SubKills.count(Reg) == 0) {
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MI->addRegisterKilled(Reg, RegInfo, true);
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return;
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}
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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addRegisterKills(SubReg, MI, SubKills);
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}
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/// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
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/// if:
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///
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/// - The register has no sub-registers and the machine instruction is the
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/// last def/use of the register, or
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/// - The register has sub-registers and none of them are killed elsewhere.
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///
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/// SubKills is filled with the set of sub-registers that are killed elsewhere.
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
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SmallSet<unsigned, 4> &SubKills) {
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const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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for (; unsigned SubReg = *SubRegs; ++SubRegs) {
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const MachineInstr *LastRef = PhysRegInfo[SubReg];
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if (LastRef != RefMI ||
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!HandlePhysRegKill(SubReg, RefMI, SubKills))
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SubKills.insert(SubReg);
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}
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if (*SubRegs == 0) {
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// No sub-registers, just check if reg is killed by RefMI.
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if (PhysRegInfo[Reg] == RefMI)
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return true;
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} else if (SubKills.empty()) {
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// None of the sub-registers are killed elsewhere.
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return true;
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}
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return false;
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}
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/// HandlePhysRegKill - Returns true if the whole register is killed in the
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/// machine instruction. If only some of its sub-registers are killed in this
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/// machine instruction, then mark those as killed and return false.
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bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
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SmallSet<unsigned, 4> SubKills;
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if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
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// This machine instruction kills this register.
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RefMI->addRegisterKilled(Reg, RegInfo, true);
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return true;
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}
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// Some sub-registers are killed by another machine instruction.
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for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs)
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addRegisterKills(SubReg, RefMI, SubKills);
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return false;
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}
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void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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// Does this kill a previous version of this register?
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if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
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if (PhysRegUsed[Reg]) {
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if (!HandlePhysRegKill(Reg, LastRef)) {
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if (PhysRegPartUse[Reg])
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PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
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}
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} else if (PhysRegPartUse[Reg]) {
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// Add implicit use / kill to last partial use.
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PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
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} else if (LastRef != MI) {
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// Defined, but not used. However, watch out for cases where a super-reg
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// is also defined on the same MI.
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LastRef->addRegisterDead(Reg, RegInfo);
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}
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}
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
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if (PhysRegUsed[SubReg]) {
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if (!HandlePhysRegKill(SubReg, LastRef)) {
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if (PhysRegPartUse[SubReg])
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PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
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}
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} else if (PhysRegPartUse[SubReg]) {
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// Add implicit use / kill to last use of a sub-register.
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PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
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} else if (LastRef != MI) {
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// This must be a def of the subreg on the same MI.
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LastRef->addRegisterDead(SubReg, RegInfo);
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}
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}
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}
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if (MI) {
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for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
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unsigned SuperReg = *SuperRegs; ++SuperRegs) {
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if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
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// The larger register is previously defined. Now a smaller part is
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// being re-defined. Treat it as read/mod/write.
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// EAX =
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// AX = EAX<imp-use,kill>, EAX<imp-def>
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MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
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true/*IsImp*/,true/*IsKill*/));
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MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
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true/*IsImp*/));
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PhysRegInfo[SuperReg] = MI;
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PhysRegUsed[SuperReg] = false;
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PhysRegPartUse[SuperReg] = NULL;
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} else {
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// Remember this partial def.
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PhysRegPartDef[SuperReg].push_back(MI);
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}
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}
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PhysRegInfo[Reg] = MI;
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PhysRegUsed[Reg] = false;
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PhysRegPartDef[Reg].clear();
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PhysRegPartUse[Reg] = NULL;
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for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
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unsigned SubReg = *SubRegs; ++SubRegs) {
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PhysRegInfo[SubReg] = MI;
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PhysRegUsed[SubReg] = false;
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PhysRegPartDef[SubReg].clear();
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PhysRegPartUse[SubReg] = NULL;
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}
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}
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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RegInfo = MF->getTarget().getRegisterInfo();
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MachineRegisterInfo& MRI = mf.getRegInfo();
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assert(RegInfo && "Target doesn't have register information?");
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ReservedRegisters = RegInfo->getReservedRegs(mf);
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unsigned NumRegs = RegInfo->getNumRegs();
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PhysRegInfo = new MachineInstr*[NumRegs];
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PhysRegUsed = new bool[NumRegs];
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PhysRegPartUse = new MachineInstr*[NumRegs];
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PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
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PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
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std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
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std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
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std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
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/// Get some space for a respectable number of registers.
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VirtRegInfo.resize(64);
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analyzePHINodes(mf);
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// Calculate live variable information in depth first order on the CFG of the
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// function. This guarantees that we will see the definition of a virtual
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// register before its uses due to dominance properties of SSA (except for PHI
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// nodes, which are treated as a special case).
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MachineBasicBlock *Entry = MF->begin();
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SmallPtrSet<MachineBasicBlock*,16> Visited;
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for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
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DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
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DFI != E; ++DFI) {
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MachineBasicBlock *MBB = *DFI;
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// Mark live-in registers as live-in.
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for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
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EE = MBB->livein_end(); II != EE; ++II) {
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assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
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"Cannot have a live-in virtual register!");
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HandlePhysRegDef(*II, 0);
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}
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// Loop over all of the instructions, processing them.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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MachineInstr *MI = I;
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// Process all of the operands of the instruction...
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unsigned NumOperandsToProcess = MI->getNumOperands();
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|
|
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
|
|
// of the uses. They will be handled in other basic blocks.
|
|
if (MI->getOpcode() == TargetInstrInfo::PHI)
|
|
NumOperandsToProcess = 1;
|
|
|
|
// Process all uses.
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
|
|
unsigned MOReg = MO.getReg();
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(MOReg))
|
|
HandleVirtRegUse(MOReg, MBB, MI);
|
|
else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
|
|
!ReservedRegisters[MOReg])
|
|
HandlePhysRegUse(MOReg, MI);
|
|
}
|
|
}
|
|
|
|
// Process all defs.
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
|
|
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
|
|
unsigned MOReg = MO.getReg();
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
|
|
VarInfo &VRInfo = getVarInfo(MOReg);
|
|
|
|
if (VRInfo.AliveBlocks.none())
|
|
// If vr is not alive in any block, then defaults to dead.
|
|
VRInfo.Kills.push_back(MI);
|
|
} else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
|
|
!ReservedRegisters[MOReg]) {
|
|
HandlePhysRegDef(MOReg, MI);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Handle any virtual assignments from PHI nodes which might be at the
|
|
// bottom of this basic block. We check all of our successor blocks to see
|
|
// if they have PHI nodes, and if so, we simulate an assignment at the end
|
|
// of the current block.
|
|
if (!PHIVarInfo[MBB->getNumber()].empty()) {
|
|
SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
|
|
|
|
for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
|
|
E = VarInfoVec.end(); I != E; ++I)
|
|
// Mark it alive only in the block we are representing.
|
|
MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
|
|
MBB);
|
|
}
|
|
|
|
// Finally, if the last instruction in the block is a return, make sure to
|
|
// mark it as using all of the live-out values in the function.
|
|
if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
|
|
MachineInstr *Ret = &MBB->back();
|
|
|
|
for (MachineRegisterInfo::liveout_iterator
|
|
I = MF->getRegInfo().liveout_begin(),
|
|
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
|
|
assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
|
|
"Cannot have a live-in virtual register!");
|
|
HandlePhysRegUse(*I, Ret);
|
|
|
|
// Add live-out registers as implicit uses.
|
|
if (Ret->findRegisterUseOperandIdx(*I) == -1)
|
|
Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
|
|
}
|
|
}
|
|
|
|
// Loop over PhysRegInfo, killing any registers that are available at the
|
|
// end of the basic block. This also resets the PhysRegInfo map.
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
if (PhysRegInfo[i])
|
|
HandlePhysRegDef(i, 0);
|
|
|
|
// Clear some states between BB's. These are purely local information.
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
PhysRegPartDef[i].clear();
|
|
|
|
std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
|
|
std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
|
|
std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
|
|
}
|
|
|
|
// Convert and transfer the dead / killed information we have gathered into
|
|
// VirtRegInfo onto MI's.
|
|
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
|
|
for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
|
|
if (VirtRegInfo[i].Kills[j] ==
|
|
MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
|
|
VirtRegInfo[i]
|
|
.Kills[j]->addRegisterDead(i +
|
|
TargetRegisterInfo::FirstVirtualRegister,
|
|
RegInfo);
|
|
else
|
|
VirtRegInfo[i]
|
|
.Kills[j]->addRegisterKilled(i +
|
|
TargetRegisterInfo::FirstVirtualRegister,
|
|
RegInfo);
|
|
|
|
// Check to make sure there are no unreachable blocks in the MC CFG for the
|
|
// function. If so, it is due to a bug in the instruction selector or some
|
|
// other part of the code generator if this happens.
|
|
#ifndef NDEBUG
|
|
for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
|
|
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
|
|
#endif
|
|
|
|
delete[] PhysRegInfo;
|
|
delete[] PhysRegUsed;
|
|
delete[] PhysRegPartUse;
|
|
delete[] PhysRegPartDef;
|
|
delete[] PHIVarInfo;
|
|
|
|
return false;
|
|
}
|
|
|
|
/// instructionChanged - When the address of an instruction changes, this method
|
|
/// should be called so that live variables can update its internal data
|
|
/// structures. This removes the records for OldMI, transfering them to the
|
|
/// records for NewMI.
|
|
void LiveVariables::instructionChanged(MachineInstr *OldMI,
|
|
MachineInstr *NewMI) {
|
|
// If the instruction defines any virtual registers, update the VarInfo,
|
|
// kill and dead information for the instruction.
|
|
for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = OldMI->getOperand(i);
|
|
if (MO.isRegister() && MO.getReg() &&
|
|
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
unsigned Reg = MO.getReg();
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
if (MO.isDef()) {
|
|
if (MO.isDead()) {
|
|
MO.setIsDead(false);
|
|
addVirtualRegisterDead(Reg, NewMI);
|
|
}
|
|
}
|
|
if (MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
addVirtualRegisterKilled(Reg, NewMI);
|
|
}
|
|
// If this is a kill of the value, update the VI kills list.
|
|
if (VI.removeKill(OldMI))
|
|
VI.Kills.push_back(NewMI); // Yes, there was a kill of it
|
|
}
|
|
}
|
|
}
|
|
|
|
/// removeVirtualRegistersKilled - Remove all killed info for the specified
|
|
/// instruction.
|
|
void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
unsigned Reg = MO.getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
assert(removed && "kill not in register's VarInfo?");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// removeVirtualRegistersDead - Remove all of the dead registers for the
|
|
/// specified instruction from the live variable information.
|
|
void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.isDead()) {
|
|
MO.setIsDead(false);
|
|
unsigned Reg = MO.getReg();
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
assert(removed && "kill not in register's VarInfo?");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
|
/// particular, we want to map the variable information of a virtual register
|
|
/// which is used in a PHI node. We map that to the BB the vreg is coming from.
|
|
///
|
|
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
|
|
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
|
|
I != E; ++I)
|
|
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
|
|
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
|
PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
|
|
.push_back(BBI->getOperand(i).getReg());
|
|
}
|