155 lines
6.7 KiB
C++
155 lines
6.7 KiB
C++
//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMISELLOWERING_H
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#define ARMISELLOWERING_H
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#include "ARMSubtarget.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include <vector>
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namespace llvm {
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class ARMConstantPoolValue;
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namespace ARMISD {
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// ARM Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
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Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
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// TargetExternalSymbol, and TargetGlobalAddress.
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WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
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CALL, // Function call.
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CALL_PRED, // Function call that's predicable.
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CALL_NOLINK, // Function call with branch not branch-and-link.
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tCALL, // Thumb function call.
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BRCOND, // Conditional branch.
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BR_JT, // Jumptable branch.
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RET_FLAG, // Return with a flag operand.
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PIC_ADD, // Add with a PC operand and a PIC label.
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CMP, // ARM compare instructions.
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CMPNZ, // ARM compare that uses only N or Z flags.
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
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FMSTAT, // ARM fmstat instruction.
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CMOV, // ARM conditional move instructions.
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CNEG, // ARM conditional negate instructions.
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FTOSI, // FP to sint within a FP register.
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FTOUI, // FP to uint within a FP register.
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SITOF, // sint to FP within a FP register.
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UITOF, // uint to FP within a FP register.
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SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
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FMRRD, // double to two gprs.
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FMDRR, // Two gprs to double.
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THREAD_POINTER
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};
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}
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//===----------------------------------------------------------------------===//
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// ARMTargetLowering - ARM Implementation of the TargetLowering interface
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class ARMTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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explicit ARMTargetLowering(TargetMachine &TM);
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
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SDOperand &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG);
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/// getPostIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if this node can be
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/// combined with a load / store to form a post-indexed load / store.
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virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SDOperand &Base, SDOperand &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG);
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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const APInt &Mask,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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virtual const TargetSubtarget* getSubtarget() {
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return static_cast<const TargetSubtarget*>(Subtarget);
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}
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private:
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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/// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
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///
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unsigned ARMPCLabelIndex;
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SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG);
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SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
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SelectionDAG &DAG);
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SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
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SDOperand Source, unsigned Size,
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unsigned Align, SelectionDAG &DAG);
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};
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}
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#endif // ARMISELLOWERING_H
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