457 lines
14 KiB
C++
457 lines
14 KiB
C++
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "MipsInstrInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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// TODO: Add the subtarget support on this constructor
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
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TM(tm), RI(*this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImmediate() && op.getImm() == 0;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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bool MipsInstrInfo::
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isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const
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{
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// addu $dst, $src, $zero || addu $dst, $zero, $src
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// or $dst, $src, $zero || or $dst, $zero, $src
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if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR))
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{
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if (MI.getOperand(1).getReg() == Mips::ZERO) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand(2).getReg() == Mips::ZERO) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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// addiu $dst, $src, 0
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if (MI.getOpcode() == Mips::ADDiu)
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{
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if ((MI.getOperand(1).isRegister()) && (isZeroImm(MI.getOperand(2)))) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsInstrInfo::
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isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const
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{
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if (MI->getOpcode() == Mips::LW)
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{
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if ((MI->getOperand(2).isFrameIndex()) && // is a stack slot
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(MI->getOperand(1).isImmediate()) && // the imm is zero
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(isZeroImm(MI->getOperand(1))))
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{
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsInstrInfo::
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isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const
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{
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if (MI->getOpcode() == Mips::SW) {
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if ((MI->getOperand(0).isFrameIndex()) && // is a stack slot
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(MI->getOperand(1).isImmediate()) && // the imm is zero
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(isZeroImm(MI->getOperand(1))))
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{
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(2).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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BuildMI(MBB, MI, get(Mips::NOP));
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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/// GetCondFromBranchOpc - Return the Mips CC that matches
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/// the correspondent Branch instruction opcode.
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static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
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{
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switch (BrOpc) {
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default: return Mips::COND_INVALID;
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case Mips::BEQ : return Mips::COND_E;
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case Mips::BNE : return Mips::COND_NE;
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case Mips::BGTZ : return Mips::COND_GZ;
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case Mips::BGEZ : return Mips::COND_GEZ;
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case Mips::BLTZ : return Mips::COND_LZ;
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case Mips::BLEZ : return Mips::COND_LEZ;
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}
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}
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/// GetCondBranchFromCond - Return the Branch instruction
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/// opcode that matches the cc.
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unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
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{
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case Mips::COND_E : return Mips::BEQ;
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case Mips::COND_NE : return Mips::BNE;
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case Mips::COND_GZ : return Mips::BGTZ;
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case Mips::COND_GEZ : return Mips::BGEZ;
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case Mips::COND_LZ : return Mips::BLTZ;
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case Mips::COND_LEZ : return Mips::BLEZ;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified
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/// condition, e.g. turning COND_E to COND_NE.
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Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
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{
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case Mips::COND_E : return Mips::COND_NE;
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case Mips::COND_NE : return Mips::COND_E;
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case Mips::COND_GZ : return Mips::COND_LEZ;
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case Mips::COND_GEZ : return Mips::COND_LZ;
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case Mips::COND_LZ : return Mips::COND_GEZ;
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case Mips::COND_LEZ : return Mips::COND_GZ;
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}
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const
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{
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (!LastInst->getDesc().isBranch())
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return true;
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// Unconditional branch
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if (LastOpc == Mips::J) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
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if (BranchCode == Mips::COND_INVALID)
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return true; // Can't handle indirect branch.
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// Conditional branch
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// Block ends with fall-through condbranch.
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if (LastOpc != Mips::COND_INVALID) {
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int LastNumOp = LastInst->getNumOperands();
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TBB = LastInst->getOperand(LastNumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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for (int i=0; i<LastNumOp-1; i++) {
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Cond.push_back(LastInst->getOperand(i));
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}
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return false;
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}
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
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if (SecondLastOpc != Mips::COND_INVALID && LastOpc == Mips::J) {
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int SecondNumOp = SecondLastInst->getNumOperands();
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TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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for (int i=0; i<SecondNumOp-1; i++) {
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Cond.push_back(SecondLastInst->getOperand(i));
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}
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The last
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// one is not executed, so remove it.
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if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned MipsInstrInfo::
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InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond)
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const
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{
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
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"Mips branch conditions can have two|three components!");
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if (FBB == 0) { // One way branch.
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if (Cond.empty()) {
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// Unconditional branch?
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BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
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} else {
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// Conditional branch.
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unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
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const TargetInstrDesc &TID = get(Opc);
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if (TID.getNumOperands() == 3)
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BuildMI(&MBB, TID).addReg(Cond[1].getReg())
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.addReg(Cond[2].getReg())
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.addMBB(TBB);
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else
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BuildMI(&MBB, TID).addReg(Cond[1].getReg())
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.addMBB(TBB);
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}
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return 1;
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}
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// Two-way Conditional branch.
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unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
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const TargetInstrDesc &TID = get(Opc);
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if (TID.getNumOperands() == 3)
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BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
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.addMBB(TBB);
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else
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BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
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BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
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return 2;
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}
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void MipsInstrInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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if (DestRC != SrcRC) {
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cerr << "Not yet supported!";
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abort();
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}
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if (DestRC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg);
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else
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assert (0 && "Can't copy this register");
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}
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void MipsInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
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.addImm(0).addFrameIndex(FI);
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else
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assert(0 && "Can't store this register to stack slot");
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}
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void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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if (RC != Mips::CPURegsRegisterClass)
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assert(0 && "Can't store this register");
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MachineInstrBuilder MIB = BuildMI(get(Mips::SW))
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.addReg(SrcReg, false, false, isKill);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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void MipsInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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if (RC != Mips::CPURegsRegisterClass)
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assert(0 && "Can't load this register");
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MachineInstrBuilder MIB = BuildMI(get(Mips::LW), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImm());
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else
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MIB.addFrameIndex(MO.getIndex());
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}
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NewMIs.push_back(MIB);
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return;
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}
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MachineInstr *MipsInstrInfo::
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foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops, int FI) const
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{
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if (Ops.size() != 1) return NULL;
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode())
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{
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case Mips::ADDu:
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if ((MI->getOperand(0).isRegister()) &&
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(MI->getOperand(1).isRegister()) &&
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(MI->getOperand(1).getReg() == Mips::ZERO) &&
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(MI->getOperand(2).isRegister()))
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{
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if (Ops[0] == 0) // COPY -> STORE
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NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
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.addImm(0).addReg(MI->getOperand(2).getReg());
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else // COPY -> LOAD
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NewMI = BuildMI(get(Mips::LW), MI->getOperand(0)
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.getReg()).addImm(0).addFrameIndex(FI);
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}
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break;
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}
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if (NewMI)
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NewMI->copyKillDeadInfo(MI);
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return NewMI;
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}
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unsigned MipsInstrInfo::
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RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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if (I->getOpcode() != Mips::J &&
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GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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/// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
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/// fall-through into its successor block.
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bool MipsInstrInfo::
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BlockHasNoFallThrough(MachineBasicBlock &MBB) const
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{
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case Mips::RET: // Return.
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case Mips::JR: // Indirect branch.
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case Mips::J: // Uncond branch.
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return true;
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default: return false;
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}
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}
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/// ReverseBranchCondition - Return the inverse opcode of the
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/// specified Branch instruction.
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bool MipsInstrInfo::
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ReverseBranchCondition(std::vector<MachineOperand> &Cond) const
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{
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assert( (Cond.size() == 3 || Cond.size() == 2) &&
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"Invalid Mips branch condition!");
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Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
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return false;
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}
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