188 lines
5.4 KiB
LLVM
188 lines
5.4 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=R600,FUNC %s
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; BFI_INT Definition pattern from ISA docs
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; (y & x) | (z & ~x)
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;
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; FUNC-LABEL: {{^}}bfi_def:
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; R600: BFI_INT
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; GCN: v_bfi_b32
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define amdgpu_kernel void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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%0 = xor i32 %x, -1
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%1 = and i32 %z, %0
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%2 = and i32 %y, %x
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%3 = or i32 %1, %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; SHA-256 Ch function
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; z ^ (x & (y ^ z))
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; FUNC-LABEL: {{^}}bfi_sha256_ch:
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; R600: BFI_INT
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; GCN: v_bfi_b32
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define amdgpu_kernel void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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%0 = xor i32 %y, %z
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%1 = and i32 %x, %0
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%2 = xor i32 %z, %1
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; SHA-256 Ma function
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; ((x & z) | (y & (x | z)))
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; FUNC-LABEL: {{^}}bfi_sha256_ma:
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; R600: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
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; R600: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
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; GCN: v_xor_b32_e32 [[DST:v[0-9]+]], {{s[0-9]+, v[0-9]+}}
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; GCN: v_bfi_b32 {{v[0-9]+}}, [[DST]], {{s[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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%0 = and i32 %x, %z
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%1 = or i32 %x, %z
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%2 = and i32 %y, %1
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%3 = or i32 %0, %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_bitselect_v2i32_pat1:
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; GCN: s_waitcnt
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; GCN-NEXT: v_bfi_b32 v0, v2, v0, v4
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; GCN-NEXT: v_bfi_b32 v1, v3, v1, v5
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; GCN-NEXT: s_setpc_b64
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define <2 x i32> @v_bitselect_v2i32_pat1(<2 x i32> %a, <2 x i32> %b, <2 x i32> %mask) {
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%xor.0 = xor <2 x i32> %a, %mask
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%and = and <2 x i32> %xor.0, %b
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%bitselect = xor <2 x i32> %and, %mask
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ret <2 x i32> %bitselect
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}
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; FUNC-LABEL: {{^}}v_bitselect_i64_pat_0:
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; GCN: s_waitcnt
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; GCN-NEXT: v_bfi_b32 v1, v1, v3, v5
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; GCN-NEXT: v_bfi_b32 v0, v0, v2, v4
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; GCN-NEXT: s_setpc_b64
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define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
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%and0 = and i64 %a, %b
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%not.a = xor i64 %a, -1
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%and1 = and i64 %not.a, %mask
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%bitselect = or i64 %and0, %and1
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ret i64 %bitselect
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}
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; FUNC-LABEL: {{^}}v_bitselect_i64_pat_1:
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; GCN: s_waitcnt
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; GCN-NEXT: v_bfi_b32 v1, v3, v1, v5
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; GCN-NEXT: v_bfi_b32 v0, v2, v0, v4
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; GCN-NEXT: s_setpc_b64
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define i64 @v_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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ret i64 %bitselect
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}
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; FUNC-LABEL: {{^}}v_bitselect_i64_pat_2:
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; GCN: s_waitcnt
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; GCN-DAG: v_bfi_b32 v0, v2, v0, v4
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; GCN-DAG: v_bfi_b32 v1, v3, v1, v5
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; GCN-NEXT: s_setpc_b64
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define i64 @v_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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ret i64 %bitselect
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}
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; FUNC-LABEL: {{^}}v_bfi_sha256_ma_i64:
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; GCN-DAG: v_xor_b32_e32 v1, v1, v3
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; GCN-DAG: v_xor_b32_e32 v0, v0, v2
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; GCN-DAG: v_bfi_b32 v1, v1, v5, v3
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; GCN-DAG: v_bfi_b32 v0, v0, v4, v2
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define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
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entry:
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%and0 = and i64 %x, %z
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%or0 = or i64 %x, %z
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%and1 = and i64 %y, %or0
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%or1 = or i64 %and0, %and1
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ret i64 %or1
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}
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; FIXME: Should leave as 64-bit SALU ops
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; FUNC-LABEL: {{^}}s_bitselect_i64_pat_0:
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_bfi_b32
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; GCN-DAG: v_bfi_b32
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define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
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%and0 = and i64 %a, %b
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%not.a = xor i64 %a, -1
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%and1 = and i64 %not.a, %mask
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%bitselect = or i64 %and0, %and1
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%scalar.use = add i64 %bitselect, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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; FUNC-LABEL: {{^}}s_bitselect_i64_pat_1:
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_bfi_b32
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; GCN-DAG: v_bfi_b32
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define amdgpu_kernel void @s_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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%scalar.use = add i64 %bitselect, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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; FUNC-LABEL: {{^}}s_bitselect_i64_pat_2:
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_bfi_b32
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_bfi_b32
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define amdgpu_kernel void @s_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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%scalar.use = add i64 %bitselect, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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; FUNC-LABEL: {{^}}s_bfi_sha256_ma_i64:
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; GCN: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_xor_b32
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; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s
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; GCN-DAG: v_xor_b32
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; GCN-DAG: v_bfi_b32
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; GCN: v_bfi_b32
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define amdgpu_kernel void @s_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
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entry:
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%and0 = and i64 %x, %z
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%or0 = or i64 %x, %z
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%and1 = and i64 %y, %or0
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%or1 = or i64 %and0, %and1
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%scalar.use = add i64 %or1, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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