266 lines
10 KiB
LLVM
266 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; SelectionDAG builder was using the IR value kind to decide how to
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; split the types for copyToRegs/copyFromRegs in all contexts. This
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; was incorrect if the ABI-like value such as a call was used outside
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; of the block. The value in that case is not used directly, but
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; through another set of copies to potentially different register
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; types in the parent block.
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; This would then end up producing inconsistent pairs of copies with
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; the wrong sizes when the vector type result from the call was split
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; into multiple pieces, but expected to be a single register in the
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; cross-block copy.
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;
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; This isn't exactly ideal for AMDGPU, since in reality the
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; intermediate vector register type is undesirable anyway, but it
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; requires more work to be able to split all vector copies in all
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; contexts.
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;
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; This was only an issue if the value was used directly in another
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; block. If there was an intermediate operation or a phi it was fine,
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; since that didn't look like an ABI copy.
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define float @call_split_type_used_outside_block_v2f32() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_v2f32:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_writelane_b32 v32, s34, 2
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; GCN-NEXT: v_writelane_b32 v32, s30, 0
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func_v2f32@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func_v2f32@rel32@hi+4
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; GCN-NEXT: v_writelane_b32 v32, s31, 1
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: v_readlane_b32 s4, v32, 0
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; GCN-NEXT: v_readlane_b32 s5, v32, 1
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: v_readlane_b32 s34, v32, 2
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; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[6:7]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[4:5]
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bb0:
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%split.ret.type = call <2 x float> @func_v2f32()
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br label %bb1
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bb1:
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%extract = extractelement <2 x float> %split.ret.type, i32 0
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ret float %extract
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}
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define float @call_split_type_used_outside_block_v3f32() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_v3f32:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_writelane_b32 v32, s34, 2
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; GCN-NEXT: v_writelane_b32 v32, s30, 0
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func_v3f32@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func_v3f32@rel32@hi+4
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; GCN-NEXT: v_writelane_b32 v32, s31, 1
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: v_readlane_b32 s4, v32, 0
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; GCN-NEXT: v_readlane_b32 s5, v32, 1
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: v_readlane_b32 s34, v32, 2
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; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[6:7]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[4:5]
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bb0:
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%split.ret.type = call <3 x float> @func_v3f32()
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br label %bb1
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bb1:
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%extract = extractelement <3 x float> %split.ret.type, i32 0
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ret float %extract
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}
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define half @call_split_type_used_outside_block_v4f16() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_v4f16:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_writelane_b32 v32, s34, 2
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; GCN-NEXT: v_writelane_b32 v32, s30, 0
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func_v4f16@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func_v4f16@rel32@hi+4
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; GCN-NEXT: v_writelane_b32 v32, s31, 1
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: v_readlane_b32 s4, v32, 0
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; GCN-NEXT: v_readlane_b32 s5, v32, 1
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: v_readlane_b32 s34, v32, 2
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; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[6:7]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[4:5]
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bb0:
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%split.ret.type = call <4 x half> @func_v4f16()
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br label %bb1
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bb1:
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%extract = extractelement <4 x half> %split.ret.type, i32 0
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ret half %extract
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}
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define { i32, half } @call_split_type_used_outside_block_struct() #0 {
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; GCN-LABEL: call_split_type_used_outside_block_struct:
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; GCN: ; %bb.0: ; %bb0
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_or_saveexec_b64 s[4:5], -1
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; GCN-NEXT: buffer_store_dword v32, off, s[0:3], s32 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_writelane_b32 v32, s34, 2
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; GCN-NEXT: v_writelane_b32 v32, s30, 0
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: s_add_u32 s32, s32, 0x400
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func_struct@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func_struct@rel32@hi+4
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; GCN-NEXT: v_writelane_b32 v32, s31, 1
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: v_readlane_b32 s4, v32, 0
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; GCN-NEXT: v_readlane_b32 s5, v32, 1
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; GCN-NEXT: v_mov_b32_e32 v1, v4
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; GCN-NEXT: s_sub_u32 s32, s32, 0x400
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; GCN-NEXT: v_readlane_b32 s34, v32, 2
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; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GCN-NEXT: buffer_load_dword v32, off, s[0:3], s32 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[6:7]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[4:5]
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bb0:
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%split.ret.type = call { <4 x i32>, <4 x half> } @func_struct()
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br label %bb1
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bb1:
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%val0 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 0
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%val1 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 1
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%extract0 = extractelement <4 x i32> %val0, i32 0
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%extract1 = extractelement <4 x half> %val1, i32 0
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%ins0 = insertvalue { i32, half } undef, i32 %extract0, 0
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%ins1 = insertvalue { i32, half } %ins0, half %extract1, 1
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ret { i32, half } %ins1
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}
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define amdgpu_kernel void @v3i16_registers(i1 %cond) #0 {
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; GCN-LABEL: v3i16_registers:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
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; GCN-NEXT: s_mov_b32 s33, s9
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s33
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_mov_b32 s32, s33
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s4, 1, s4
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; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 1
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; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
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; GCN-NEXT: s_cbranch_vccz BB4_2
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; GCN-NEXT: ; %bb.1:
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; GCN-NEXT: s_mov_b32 s4, 0
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; GCN-NEXT: s_mov_b32 s5, s4
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: s_branch BB4_3
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; GCN-NEXT: BB4_2: ; %if.else
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func_v3i16@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func_v3i16@rel32@hi+4
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: BB4_3: ; %if.end
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; GCN-NEXT: global_store_short v[0:1], v1, off
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_endpgm
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entry:
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br i1 %cond, label %if.then, label %if.else
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if.then: ; preds = %entry
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br label %if.end
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if.else: ; preds = %entry
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%call6 = tail call <3 x i16> @func_v3i16() #0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%call6.sink = phi <3 x i16> [ %call6, %if.else ], [ undef, %if.then ]
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store <3 x i16> %call6.sink, <3 x i16> addrspace(1)* undef
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ret void
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}
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define amdgpu_kernel void @v3f16_registers(i1 %cond) #0 {
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; GCN-LABEL: v3f16_registers:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s4, s[4:5], 0x0
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; GCN-NEXT: s_mov_b32 s33, s9
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s33
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_mov_b32 s32, s33
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s4, 1, s4
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; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], s4, 1
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; GCN-NEXT: s_and_b64 vcc, exec, s[4:5]
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; GCN-NEXT: s_cbranch_vccz BB5_2
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; GCN-NEXT: ; %bb.1:
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; GCN-NEXT: s_mov_b32 s4, 0
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; GCN-NEXT: s_mov_b32 s5, s4
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: v_mov_b32_e32 v1, s5
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; GCN-NEXT: s_branch BB5_3
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; GCN-NEXT: BB5_2: ; %if.else
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, func_v3f16@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, func_v3f16@rel32@hi+4
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: BB5_3: ; %if.end
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; GCN-NEXT: global_store_short v[0:1], v1, off
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; GCN-NEXT: global_store_dword v[0:1], v0, off
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; GCN-NEXT: s_endpgm
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entry:
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br i1 %cond, label %if.then, label %if.else
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if.then: ; preds = %entry
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br label %if.end
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if.else: ; preds = %entry
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%call6 = tail call <3 x half> @func_v3f16() #0
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%call6.sink = phi <3 x half> [ %call6, %if.else ], [ undef, %if.then ]
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store <3 x half> %call6.sink, <3 x half> addrspace(1)* undef
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ret void
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}
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declare hidden <2 x float> @func_v2f32() #0
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declare hidden <3 x float> @func_v3f32() #0
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declare hidden <4 x float> @func_v4f32() #0
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declare hidden <4 x half> @func_v4f16() #0
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declare hidden <3 x i16> @func_v3i16()
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declare hidden <3 x half> @func_v3f16()
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declare hidden { <4 x i32>, <4 x half> } @func_struct() #0
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attributes #0 = { nounwind}
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