293 lines
13 KiB
LLVM
293 lines
13 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
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;CHECK-LABEL: {{^}}buffer_load:
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;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
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;CHECK: buffer_load_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
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;CHECK: buffer_load_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
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%data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
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%data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs:
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;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
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;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc
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;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], [[OFFSET]] idxen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 4, i32 8188, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_idx:
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;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs:
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;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
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;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
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main_body:
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%ofs = add i32 %1, 60
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_both:
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;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_both_reversed:
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;CHECK: v_mov_b32_e32 v2, v0
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;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x1:
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;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
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ret float %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x2:
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;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
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ret <2 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_negative_offset:
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;CHECK: v_add_{{[iu]}}32_e32 {{v[0-9]+}}, vcc, -16, v0
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;CHECK: buffer_load_dwordx4 v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 idxen offen
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define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
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main_body:
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%ofs.1 = add i32 %ofs, -16
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%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i32 0, i32 0)
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ret <4 x float> %data
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}
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; SI won't merge ds memory operations, because of the signed offset bug, so
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; we only have check lines for VI.
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; CHECK-LABEL: buffer_load_mmo:
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; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
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define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) {
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entry:
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store float 0.0, float addrspace(3)* %lds
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%val = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
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%tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4
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store float 0.0, float addrspace(3)* %tmp2
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ret float %val
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}
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;CHECK-LABEL: {{^}}buffer_load_int:
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;CHECK: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
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;CHECK: buffer_load_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc
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;CHECK: buffer_load_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {
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main_body:
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%data = call <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
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%data_glc = call <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
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%data_slc = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
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%fdata = bitcast <4 x i32> %data to <4 x float>
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%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
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%fdata_slc = bitcast i32 %data_slc to float
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%r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
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%r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
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%r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
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ret {<4 x float>, <2 x float>, float} %r2
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_ubyte:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @struct_buffer_load_ubyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
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%tmp2 = zext i8 %tmp to i32
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%val = uitofp i32 %tmp2 to float
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ret float %val
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_ushort:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
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;CHECK-NEXT: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @struct_buffer_load_ushort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
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%tmp2 = zext i16 %tmp to i32
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%val = uitofp i32 %tmp2 to float
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ret float %val
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_sbyte:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
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;CHECK-NEXT: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @struct_buffer_load_sbyte(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%tmp = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
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%tmp2 = sext i8 %tmp to i32
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%val = sitofp i32 %tmp2 to float
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ret float %val
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_sshort:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, v[0:1], s[0:3], 0 idxen offen
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;CHECK-NEXT: s_waitcnt vmcnt(0)
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;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
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;CHECK-NEXT: ; return to shader part epilog
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define amdgpu_ps float @struct_buffer_load_sshort(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%tmp = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 0, i32 0)
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%tmp2 = sext i16 %tmp to i32
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%val = sitofp i32 %tmp2 to float
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ret float %val
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_f16:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: ds_write_b16 v0, [[VAL]]
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define amdgpu_ps void @struct_buffer_load_f16(<4 x i32> inreg %rsrc, half addrspace(3)* %ptr, i32 %idx) {
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main_body:
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%val = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
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store half %val, half addrspace(3)* %ptr
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ret void
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_v2f16:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: ds_write_b32 v0, [[VAL]]
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define amdgpu_ps void @struct_buffer_load_v2f16(<4 x i32> inreg %rsrc, <2 x half> addrspace(3)* %ptr, i32 %idx) {
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main_body:
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%val = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
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store <2 x half> %val, <2 x half> addrspace(3)* %ptr
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ret void
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_v4f16:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: ds_write_b64 v0, [[VAL]]
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define amdgpu_ps void @struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, <4 x half> addrspace(3)* %ptr, i32 %idx) {
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main_body:
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%val = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
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store <4 x half> %val, <4 x half> addrspace(3)* %ptr
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ret void
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_i16:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: ds_write_b16 v0, [[VAL]]
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define amdgpu_ps void @struct_buffer_load_i16(<4 x i32> inreg %rsrc, i16 addrspace(3)* %ptr, i32 %idx) {
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main_body:
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%val = call i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
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store i16 %val, i16 addrspace(3)* %ptr
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ret void
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_v2i16:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], v1, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: ds_write_b32 v0, [[VAL]]
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define amdgpu_ps void @struct_buffer_load_v2i16(<4 x i32> inreg %rsrc, <2 x i16> addrspace(3)* %ptr, i32 %idx) {
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main_body:
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%val = call <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
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store <2 x i16> %val, <2 x i16> addrspace(3)* %ptr
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ret void
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_v4i16:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], v1, s[0:3], 0 idxen
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: ds_write_b64 v0, [[VAL]]
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define amdgpu_ps void @struct_buffer_load_v4i16(<4 x i32> inreg %rsrc, <4 x i16> addrspace(3)* %ptr, i32 %idx) {
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main_body:
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%val = call <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32> %rsrc, i32 %idx, i32 0, i32 0, i32 0)
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store <4 x i16> %val, <4 x i16> addrspace(3)* %ptr
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ret void
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}
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declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) #0
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declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #0
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declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #0
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declare i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32>, i32, i32, i32, i32) #0
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declare <2 x i32> @llvm.amdgcn.struct.buffer.load.v2i32(<4 x i32>, i32, i32, i32, i32) #0
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declare <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #0
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32) #0
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declare half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32>, i32, i32, i32, i32) #0
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declare <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) #0
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declare <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) #0
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declare i16 @llvm.amdgcn.struct.buffer.load.i16(<4 x i32>, i32, i32, i32, i32) #0
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declare <2 x i16> @llvm.amdgcn.struct.buffer.load.v2i16(<4 x i32>, i32, i32, i32, i32) #0
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declare <4 x i16> @llvm.amdgcn.struct.buffer.load.v4i16(<4 x i32>, i32, i32, i32, i32) #0
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attributes #0 = { nounwind readonly }
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