127 lines
4.0 KiB
LLVM
127 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
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; ===================================================================================
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; V_OR3_B32
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; ===================================================================================
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define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: or3:
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; VI: ; %bb.0:
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: v_or_b32_e32 v0, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: or3:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: or3:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = or i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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; ThreeOp instruction variant not used due to Constant Bus Limitations
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; TODO: with reassociation it is possible to replace a v_or_b32_e32 with an s_or_b32
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define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {
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; VI-LABEL: or3_vgpr_a:
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; VI: ; %bb.0:
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; VI-NEXT: v_or_b32_e32 v0, s2, v0
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; VI-NEXT: v_or_b32_e32 v0, s3, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: or3_vgpr_a:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
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; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: or3_vgpr_a:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, v0, s2, s3
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = or i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: or3_vgpr_all2:
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; VI: ; %bb.0:
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; VI-NEXT: v_or_b32_e32 v1, v1, v2
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: or3_vgpr_all2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: or3_vgpr_all2:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = or i32 %b, %c
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%result = or i32 %a, %x
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {
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; VI-LABEL: or3_vgpr_bc:
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; VI: ; %bb.0:
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; VI-NEXT: v_or_b32_e32 v0, s2, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: or3_vgpr_bc:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or3_b32 v0, s2, v0, v1
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: or3_vgpr_bc:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, s2, v0, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = or i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {
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; VI-LABEL: or3_vgpr_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_or_b32_e32 v0, v1, v0
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; VI-NEXT: v_or_b32_e32 v0, 64, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: or3_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: or3_vgpr_const:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: ; return to shader part epilog
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%x = or i32 64, %b
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%result = or i32 %x, %a
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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