501 lines
15 KiB
LLVM
501 lines
15 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: ; %bb.1:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {
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call void @llvm.amdgcn.kill(i1 true)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: s_cbranch_execnz BB1_2
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; CHECK-NEXT: ; %bb.1:
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; CHECK-NEXT: exp null off, off, off, off done vm
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB1_2:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
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call void @llvm.amdgcn.kill(i1 false)
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ret void
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}
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; FIXME: Ideally only one would be emitted
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg_x2:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: s_cbranch_execnz BB2_2
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK: BB2_2:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: s_cbranch_execnz BB2_4
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB2_4:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 {
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call void @llvm.amdgcn.kill(i1 false)
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call void @llvm.amdgcn.kill(i1 false)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_var:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0
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; CHECK-NEXT: s_cbranch_execnz BB3_2
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB3_2:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
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%cmp = fcmp olt float %x, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp)
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ret void
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}
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; FIXME: Ideally only one would be emitted
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; CHECK-LABEL: {{^}}test_kill_depth_var_x2_same:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0
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; CHECK-NEXT: s_cbranch_execnz BB4_2
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB4_2:
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; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0
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; CHECK-NEXT: s_cbranch_execnz BB4_4
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB4_4:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 {
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%cmp = fcmp olt float %x, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp)
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call void @llvm.amdgcn.kill(i1 %cmp)
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ret void
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}
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; FIXME: Ideally only one early-exit would be emitted
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; CHECK-LABEL: {{^}}test_kill_depth_var_x2:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0
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; CHECK-NEXT: s_cbranch_execnz BB5_2
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB5_2:
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; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v1
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; CHECK-NEXT: s_cbranch_execnz BB5_4
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; CHECK: exp null
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB5_4:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 {
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%cmp.x = fcmp olt float %x, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.x)
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%cmp.y = fcmp olt float %y, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.y)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_var_x2_instructions:
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; CHECK-NEXT: ; %bb.0:
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; CHECK-NEXT: v_cmpx_gt_f32_e32 vcc, 0, v0
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; CHECK-NEXT: s_cbranch_execnz BB6_2
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; CHECK-NEXT: ; %bb.1:
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; CHECK-NEXT: exp
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB6_2:
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7
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; CHECK-NEXT: s_cbranch_execnz BB6_4
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; CHECK-NEXT: ; %bb.3:
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; CHECK-NEXT: exp
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB6_4:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
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%cmp.x = fcmp olt float %x, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.x)
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%y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={v7}"()
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%cmp.y = fcmp olt float %y, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.y)
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ret void
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}
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; FIXME: why does the skip depend on the asm length in the same block?
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; CHECK-LABEL: {{^}}test_kill_control_flow:
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; CHECK: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; %bb.1:
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7
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; TODO: We could do an early-exit here (the branch above is uniform!)
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; CHECK-NOT: exp null
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; CHECK: v_mov_b32_e32 v0, 1.0
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define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={v7}"()
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%cmp.var = fcmp olt float %var, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.var)
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br label %exit
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exit:
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ret float 1.0
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}
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; CHECK-LABEL: {{^}}test_kill_control_flow_remainder:
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; CHECK: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; CHECK-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; %bb.1: ; %bb
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: ;;#ASMEND
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; CHECK: v_mov_b32_e64 v8, -1
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; CHECK: ;;#ASMEND
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; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7
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; TODO: We could do an early-exit here (the branch above is uniform!)
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; CHECK-NOT: exp null
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; CHECK: buffer_store_dword v8
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; CHECK: v_mov_b32_e64 v9, -2
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; CHECK: {{^}}BB{{[0-9]+_[0-9]+}}:
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; CHECK: buffer_store_dword v9
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={v7}"()
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%live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={v8}"()
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%cmp.var = fcmp olt float %var, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.var)
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store volatile float %live.across, float addrspace(1)* undef
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%live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={v9}"()
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br label %exit
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exit:
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%phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
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store float %phi, float addrspace(1)* undef
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_divergent_loop:
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; CHECK: v_cmp_eq_u32_e32 vcc, 0, v0
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; CHECK-NEXT: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], vcc
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; CHECK-NEXT: s_xor_b64 [[SAVEEXEC]], exec, [[SAVEEXEC]]
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; CHECK-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]]
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; CHECK: ; %bb.{{[0-9]+}}: ; %bb.preheader
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; CHECK: s_mov_b32
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; CHECK: [[LOOP_BB:BB[0-9]+_[0-9]+]]:
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; CHECK: v_mov_b32_e64 v7, -1
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; CHECK: v_nop_e64
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; CHECK: v_cmpx_gt_f32_e32 vcc, 0, v7
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; CHECK-NEXT: ; %bb.3:
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; CHECK: buffer_load_dword [[LOAD:v[0-9]+]]
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; CHECK: v_cmp_eq_u32_e32 vcc, 0, [[LOAD]]
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; CHECK-NEXT: s_and_b64 vcc, exec, vcc
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; CHECK-NEXT: s_cbranch_vccnz [[LOOP_BB]]
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; CHECK-NEXT: {{^}}[[EXIT]]:
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; CHECK: s_or_b64 exec, exec, [[SAVEEXEC]]
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; CHECK: buffer_store_dword
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; CHECK: s_endpgm
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define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={v7}"()
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%cmp.var = fcmp olt float %var, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.var)
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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%loop.cond = icmp eq i32 %vgpr, 0
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br i1 %loop.cond, label %bb, label %exit
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exit:
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store volatile i32 8, i32 addrspace(1)* undef
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ret void
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}
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; bug 28550
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; CHECK-LABEL: {{^}}phi_use_def_before_kill:
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; CHECK: v_cndmask_b32_e64 [[PHIREG:v[0-9]+]], 0, -1.0,
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; CHECK: v_cmpx_lt_f32_e32 vcc, 0,
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; CHECK-NEXT: s_cbranch_execnz [[BB4:BB[0-9]+_[0-9]+]]
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; CHECK: exp
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; CHECK-NEXT: s_endpgm
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; CHECK: [[KILLBB:BB[0-9]+_[0-9]+]]:
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; CHECK-NEXT: s_cbranch_scc0 [[PHIBB:BB[0-9]+_[0-9]+]]
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; CHECK: [[PHIBB]]:
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; CHECK: v_cmp_eq_f32_e32 vcc, 0, [[PHIREG]]
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; CHECK: s_cbranch_vccz [[ENDBB:BB[0-9]+_[0-9]+]]
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; CHECK: ; %bb10
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; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 9
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; CHECK: buffer_store_dword
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; CHECK: [[ENDBB]]:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @phi_use_def_before_kill(float inreg %x) #0 {
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bb:
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%tmp = fadd float %x, 1.000000e+00
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%tmp1 = fcmp olt float 0.000000e+00, %tmp
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%tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00
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%cmp.tmp2 = fcmp olt float %tmp2, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.tmp2)
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br i1 undef, label %phibb, label %bb8
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phibb:
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%tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ]
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%tmp6 = fcmp oeq float %tmp5, 0.000000e+00
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br i1 %tmp6, label %bb10, label %end
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bb8:
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store volatile i32 8, i32 addrspace(1)* undef
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br label %phibb
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bb10:
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store volatile i32 9, i32 addrspace(1)* undef
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br label %end
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end:
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ret void
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}
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; CHECK-LABEL: {{^}}no_skip_no_successors:
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; CHECK: v_cmp_nge_f32
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; CHECK: s_cbranch_vccz [[SKIPKILL:BB[0-9]+_[0-9]+]]
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; CHECK: ; %bb6
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; CHECK: s_mov_b64 exec, 0
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; CHECK: [[SKIPKILL]]:
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; CHECK: v_cmp_nge_f32_e32 vcc
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; CHECK: %bb.3: ; %bb5
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; CHECK-NEXT: .Lfunc_end{{[0-9]+}}
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define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 {
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bb:
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%tmp = fcmp ult float %arg1, 0.000000e+00
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%tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000
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br i1 %tmp, label %bb6, label %bb3
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bb3: ; preds = %bb
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br i1 %tmp2, label %bb5, label %bb4
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bb4: ; preds = %bb3
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br i1 true, label %bb5, label %bb7
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bb5: ; preds = %bb4, %bb3
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unreachable
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bb6: ; preds = %bb
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call void @llvm.amdgcn.kill(i1 false)
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unreachable
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bb7: ; preds = %bb4
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ret void
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}
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; CHECK-LABEL: {{^}}if_after_kill_block:
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; CHECK: ; %bb.0:
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; CHECK: s_and_saveexec_b64
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; CHECK: s_xor_b64
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; CHECK: v_cmpx_gt_f32_e32 vcc, 0,
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; CHECK: BB{{[0-9]+_[0-9]+}}:
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; CHECK: s_or_b64 exec, exec
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; CHECK: image_sample_c
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; CHECK: v_cmp_neq_f32_e32 vcc, 0,
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; CHECK: s_and_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc
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; CHECK-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]]
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; CHECK-NOT: branch
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; CHECK: ; %bb.{{[0-9]+}}: ; %bb8
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; CHECK: buffer_store_dword
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; CHECK: [[END]]:
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; CHECK: s_endpgm
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define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, float %arg3) #0 {
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bb:
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%tmp = fcmp ult float %arg1, 0.000000e+00
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br i1 %tmp, label %bb3, label %bb4
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bb3: ; preds = %bb
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%cmp.arg = fcmp olt float %arg, 0.0
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call void @llvm.amdgcn.kill(i1 %cmp.arg)
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br label %bb4
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bb4: ; preds = %bb3, %bb
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%tmp5 = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 16, float %arg2, float %arg3, <8 x i32> undef, <4 x i32> undef, i1 0, i32 0, i32 0)
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%tmp6 = extractelement <4 x float> %tmp5, i32 0
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%tmp7 = fcmp une float %tmp6, 0.000000e+00
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br i1 %tmp7, label %bb8, label %bb9
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bb8: ; preds = %bb9, %bb4
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store volatile i32 9, i32 addrspace(1)* undef
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ret void
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bb9: ; preds = %bb4
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ret void
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}
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; CHECK-LABEL: {{^}}cbranch_kill:
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; CHECK-NOT: exp null off, off, off, off done vm
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define amdgpu_ps void @cbranch_kill(i32 inreg %0, <2 x float> %1) {
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.entry:
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%val0 = extractelement <2 x float> %1, i32 0
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%val1 = extractelement <2 x float> %1, i32 1
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%p0 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 0, i32 immarg 1, i32 %0) #2
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%sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %p0, float %p0, float %p0, float 0.000000e+00, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0)
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%cond0 = fcmp ugt float %sample, 0.000000e+00
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br i1 %cond0, label %live, label %kill
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kill:
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call void @llvm.amdgcn.kill(i1 false)
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br label %export
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|
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live:
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%i0 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 0, i32 immarg 0, i32 %0) #2
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%i1 = call float @llvm.amdgcn.interp.p2(float %i0, float %val1, i32 immarg 0, i32 immarg 0, i32 %0) #2
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%i2 = call float @llvm.amdgcn.interp.p1(float %val0, i32 immarg 1, i32 immarg 0, i32 %0) #2
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%i3 = call float @llvm.amdgcn.interp.p2(float %i2, float %val1, i32 immarg 1, i32 immarg 0, i32 %0) #2
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%scale.i0 = fmul reassoc nnan nsz arcp contract float %i0, %sample
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%scale.i1 = fmul reassoc nnan nsz arcp contract float %i1, %sample
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%scale.i2 = fmul reassoc nnan nsz arcp contract float %i2, %sample
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%scale.i3 = fmul reassoc nnan nsz arcp contract float %i3, %sample
|
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br label %export
|
|
|
|
export:
|
|
%proxy.0.0 = phi float [ undef, %kill ], [ %scale.i0, %live ]
|
|
%proxy.0.1 = phi float [ undef, %kill ], [ %scale.i1, %live ]
|
|
%proxy.0.2 = phi float [ undef, %kill ], [ %scale.i2, %live ]
|
|
%proxy.0.3 = phi float [ undef, %kill ], [ %scale.i3, %live ]
|
|
%out.0 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %proxy.0.0, float %proxy.0.1) #2
|
|
%out.1 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %proxy.0.2, float %proxy.0.3) #2
|
|
call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> %out.0, <2 x half> %out.1, i1 immarg true, i1 immarg true) #3
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: {{^}}complex_loop:
|
|
; CHECK: s_mov_b64 exec, 0
|
|
; CHECK-NOT: exp null
|
|
define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) {
|
|
.entry:
|
|
%flaga = icmp sgt i32 %cmpa, 0
|
|
br i1 %flaga, label %.lr.ph, label %._crit_edge
|
|
|
|
.lr.ph:
|
|
br label %hdr
|
|
|
|
hdr:
|
|
%ctr = phi i32 [ 0, %.lr.ph ], [ %ctr.next, %latch ]
|
|
%flagb = icmp ugt i32 %ctr, %cmpb
|
|
br i1 %flagb, label %kill, label %latch
|
|
|
|
kill:
|
|
call void @llvm.amdgcn.kill(i1 false)
|
|
br label %latch
|
|
|
|
latch:
|
|
%ctr.next = add nuw nsw i32 %ctr, 1
|
|
%flagc = icmp slt i32 %ctr.next, %cmpc
|
|
br i1 %flagc, label %hdr, label %._crit_edge
|
|
|
|
._crit_edge:
|
|
%tmp = phi i32 [ -1, %.entry ], [ %ctr.next, %latch ]
|
|
%out = bitcast i32 %tmp to <2 x half>
|
|
call void @llvm.amdgcn.exp.compr.v2f16(i32 immarg 0, i32 immarg 15, <2 x half> %out, <2 x half> undef, i1 immarg true, i1 immarg true)
|
|
ret void
|
|
}
|
|
|
|
declare float @llvm.amdgcn.interp.p1(float, i32 immarg, i32 immarg, i32) #2
|
|
declare float @llvm.amdgcn.interp.p2(float, float, i32 immarg, i32 immarg, i32) #2
|
|
declare void @llvm.amdgcn.exp.compr.v2f16(i32 immarg, i32 immarg, <2 x half>, <2 x half>, i1 immarg, i1 immarg) #3
|
|
declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #2
|
|
declare float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 immarg, float, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
|
|
declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
|
|
declare void @llvm.amdgcn.kill(i1) #0
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readonly }
|
|
attributes #2 = { nounwind readnone speculatable }
|
|
attributes #3 = { inaccessiblememonly nounwind writeonly }
|