199 lines
5.2 KiB
LLVM
199 lines
5.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s
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; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s
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; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s
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; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-DL --check-prefix=GFX906 %s
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; GCN-LABEL: {{^}}scalar_xnor_i32_one_use
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; GCN: s_xnor_b32
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define amdgpu_kernel void @scalar_xnor_i32_one_use(
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i32 addrspace(1)* %r0, i32 %a, i32 %b) {
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entry:
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%xor = xor i32 %a, %b
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%r0.val = xor i32 %xor, -1
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_xnor_i32_mul_use
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; GCN-NOT: s_xnor_b32
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; GCN: s_xor_b32
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; GCN: s_not_b32
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; GCN: s_add_i32
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define amdgpu_kernel void @scalar_xnor_i32_mul_use(
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i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) {
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entry:
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%xor = xor i32 %a, %b
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%r0.val = xor i32 %xor, -1
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%r1.val = add i32 %xor, %a
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store i32 %r0.val, i32 addrspace(1)* %r0
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store i32 %r1.val, i32 addrspace(1)* %r1
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ret void
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}
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; GCN-LABEL: {{^}}scalar_xnor_i64_one_use
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; GCN: s_xnor_b64
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define amdgpu_kernel void @scalar_xnor_i64_one_use(
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i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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entry:
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%xor = xor i64 %a, %b
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%r0.val = xor i64 %xor, -1
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_xnor_i64_mul_use
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; GCN-NOT: s_xnor_b64
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; GCN: s_xor_b64
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; GCN: s_not_b64
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; GCN: s_add_u32
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; GCN: s_addc_u32
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define amdgpu_kernel void @scalar_xnor_i64_mul_use(
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i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) {
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entry:
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%xor = xor i64 %a, %b
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%r0.val = xor i64 %xor, -1
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%r1.val = add i64 %xor, %a
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store i64 %r0.val, i64 addrspace(1)* %r0
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store i64 %r1.val, i64 addrspace(1)* %r1
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ret void
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}
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; GCN-LABEL: {{^}}vector_xnor_i32_one_use
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; GCN-NOT: s_xnor_b32
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; GCN: v_not_b32
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; GCN: v_xor_b32
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; GCN-DL: v_xnor_b32
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define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) {
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entry:
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%xor = xor i32 %a, %b
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%r = xor i32 %xor, -1
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ret i32 %r
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}
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; GCN-LABEL: {{^}}vector_xnor_i64_one_use
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; GCN-NOT: s_xnor_b64
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; GCN: v_not_b32
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; GCN: v_not_b32
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN-DL: v_xnor_b32
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; GCN-DL: v_xnor_b32
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define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) {
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entry:
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%xor = xor i64 %a, %b
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%r = xor i64 %xor, -1
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ret i64 %r
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}
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; GCN-LABEL: {{^}}xnor_s_v_i32_one_use
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; GCN-NOT: s_xnor_b32
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; GCN: s_not_b32
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; GCN: v_xor_b32
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define amdgpu_kernel void @xnor_s_v_i32_one_use(i32 addrspace(1)* %out, i32 %s) {
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%xor = xor i32 %s, %v
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%d = xor i32 %xor, -1
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store i32 %d, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}xnor_v_s_i32_one_use
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; GCN-NOT: s_xnor_b32
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; GCN: s_not_b32
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; GCN: v_xor_b32
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define amdgpu_kernel void @xnor_v_s_i32_one_use(i32 addrspace(1)* %out, i32 %s) {
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%v = call i32 @llvm.amdgcn.workitem.id.x() #1
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%xor = xor i32 %v, %s
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%d = xor i32 %xor, -1
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store i32 %d, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}xnor_i64_s_v_one_use
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; GCN-NOT: s_xnor_b64
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; GCN: s_not_b64
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN-DL: v_xnor_b32
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; GCN-DL: v_xnor_b32
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define amdgpu_kernel void @xnor_i64_s_v_one_use(
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i64 addrspace(1)* %r0, i64 %a) {
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entry:
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%b32 = call i32 @llvm.amdgcn.workitem.id.x() #1
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%b64 = zext i32 %b32 to i64
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%b = shl i64 %b64, 29
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%xor = xor i64 %a, %b
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%r0.val = xor i64 %xor, -1
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}xnor_i64_v_s_one_use
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; GCN-NOT: s_xnor_b64
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; GCN: s_not_b64
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; GCN: v_xor_b32
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; GCN: v_xor_b32
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; GCN-DL: v_xnor_b32
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; GCN-DL: v_xnor_b32
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define amdgpu_kernel void @xnor_i64_v_s_one_use(
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i64 addrspace(1)* %r0, i64 %a) {
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entry:
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%b32 = call i32 @llvm.amdgcn.workitem.id.x() #1
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%b64 = zext i32 %b32 to i64
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%b = shl i64 %b64, 29
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%xor = xor i64 %b, %a
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%r0.val = xor i64 %xor, -1
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}vector_xor_na_b_i32_one_use
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; GCN-NOT: s_xnor_b32
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; GCN: v_not_b32
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; GCN: v_xor_b32
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; GCN-DL: v_xnor_b32
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define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) {
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entry:
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%na = xor i32 %a, -1
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%r = xor i32 %na, %b
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ret i32 %r
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}
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; GCN-LABEL: {{^}}vector_xor_a_nb_i32_one_use
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; GCN-NOT: s_xnor_b32
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; GCN: v_not_b32
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; GCN: v_xor_b32
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; GCN-DL: v_xnor_b32
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define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) {
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entry:
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%nb = xor i32 %b, -1
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%r = xor i32 %a, %nb
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ret i32 %r
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}
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; GCN-LABEL: {{^}}scalar_xor_a_nb_i64_one_use
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; GCN: s_xnor_b64
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define amdgpu_kernel void @scalar_xor_a_nb_i64_one_use(
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i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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entry:
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%nb = xor i64 %b, -1
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%r0.val = xor i64 %a, %nb
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_xor_na_b_i64_one_use
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; GCN: s_xnor_b64
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define amdgpu_kernel void @scalar_xor_na_b_i64_one_use(
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i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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entry:
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%na = xor i64 %a, -1
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%r0.val = xor i64 %na, %b
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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