40 lines
1.4 KiB
LLVM
40 lines
1.4 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
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;
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; Check the latency for instructions for both generic and cortex-r52.
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; Cortex-r52 machine model will cause the div to be sceduled before eor
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; as div takes more cycles to compute than eor.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: foo:%bb.0 entry
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; CHECK: EORrr
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; GENERIC: Latency : 1
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; R52_SCHED: Latency : 3
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; CHECK: MLA
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; GENERIC: Latency : 2
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; R52_SCHED: Latency : 4
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; CHECK: SDIV
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; GENERIC: Latency : 0
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; R52_SCHED: Latency : 8
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; CHECK: ** Final schedule for %bb.0 ***
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; GENERIC: EORrr
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; GENERIC: SDIV
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; R52_SCHED: SDIV
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; R52_SCHED: EORrr
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; CHECK: ********** INTERVALS **********
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8r-arm-none-eabi"
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; Function Attrs: norecurse nounwind readnone
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define hidden i32 @foo(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {
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entry:
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%xor = xor i32 %c, %b
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%mul = mul nsw i32 %xor, %c
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%add = add nsw i32 %mul, %a
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%div = sdiv i32 %a, %b
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%sub = sub i32 %add, %div
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ret i32 %sub
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}
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