73 lines
2.2 KiB
LLVM
73 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
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; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
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define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
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; CHECK-LABEL: test_vget_lane_f16_1:
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; CHECK: vmovx.f16 s0, s0
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; CHECK-NEXT: vcvtb.f32.f16 s0, s0
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entry:
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%elt = extractelement <4 x half> %a, i32 1
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
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; CHECK-LABEL: test_vget_lane_f16_2:
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; CHECK-NOT: vmovx.f16
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; CHECK: vcvtb.f32.f16 s0, s1
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entry:
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%elt = extractelement <4 x half> %a, i32 2
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
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; CHECK-LABEL: test_vget_laneq_f16_6:
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; CHECK-NOT: vmovx.f16
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; CHECK: vcvtb.f32.f16 s0, s3
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entry:
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%elt = extractelement <8 x half> %a, i32 6
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
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; CHECK-LABEL: test_vget_laneq_f16_7:
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; CHECK: vmovx.f16 s0, s3
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; CHECK: vcvtb.f32.f16 s0, s0
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entry:
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%elt = extractelement <8 x half> %a, i32 7
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%conv = fpext half %elt to float
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ret float %conv
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}
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define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
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; CHECK-LABEL: test_vset_lane_f16:
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; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
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; CHECK: vmov.16 d{{[0-9]+}}[3], r[[GPR]]
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <4 x half> %a, half %b, i32 3
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ret <4 x half> %x
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}
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define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
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; CHECK-LABEL: test_vset_laneq_f16_1:
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; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
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; CHECK: vmov.16 d{{[0-9]+}}[1], r[[GPR]]
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <8 x half> %a, half %b, i32 1
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ret <8 x half> %x
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}
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define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
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; CHECK-LABEL: test_vset_laneq_f16_7:
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; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
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; CHECK: vmov.16 d{{[0-9]+}}[3], r[[GPR]]
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <8 x half> %a, half %b, i32 7
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ret <8 x half> %x
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}
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