245 lines
		
	
	
		
			6.6 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			245 lines
		
	
	
		
			6.6 KiB
		
	
	
	
		
			LLVM
		
	
	
	
| ; RUN: llc -mcpu=mips32r2 -march=mipsel -relocation-model=static -o - %s | FileCheck %s
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| 
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| define void @isr_sw0() #0 {
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| ; CHECK-LABEL: isr_sw0:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, [[R1:[0-9]+]]($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, [[R2:[0-9]+]]($sp)
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| ; CHECK: ins    $27, $zero, 8, 1
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ; Must save all registers
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| ; CHECK: sw      $7, {{[0-9]+}}($sp)
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| ; CHECK: sw      $6, {{[0-9]+}}($sp)
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| ; CHECK: sw      $5, {{[0-9]+}}($sp)
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| ; CHECK: sw      $4, {{[0-9]+}}($sp)
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| ; CHECK: sw      $3, {{[0-9]+}}($sp)
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| ; CHECK: sw      $2, {{[0-9]+}}($sp)
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| ; CHECK: sw      $25, {{[0-9]+}}($sp)
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| ; CHECK: sw      $24, {{[0-9]+}}($sp)
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| ; CHECK: sw      $15, {{[0-9]+}}($sp)
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| ; CHECK: sw      $14, {{[0-9]+}}($sp)
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| ; CHECK: sw      $13, {{[0-9]+}}($sp)
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| ; CHECK: sw      $12, {{[0-9]+}}($sp)
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| ; CHECK: sw      $11, {{[0-9]+}}($sp)
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| ; CHECK: sw      $10, {{[0-9]+}}($sp)
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| ; CHECK: sw      $9, {{[0-9]+}}($sp)
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| ; CHECK: sw      $8, {{[0-9]+}}($sp)
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| ; CHECK: sw      $ra, [[R5:[0-9]+]]($sp)
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| ; CHECK: sw      $gp, {{[0-9]+}}($sp)
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| ; CHECK: sw      $1, {{[0-9]+}}($sp)
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| ; CHECK: mflo    $26
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| ; CHECK: sw      $26, [[R3:[0-9]+]]($sp)
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| ; CHECK: mfhi    $26
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| ; CHECK: sw      $26, [[R4:[0-9]+]]($sp)
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|   call void bitcast (void (...)* @write to void ()*)()
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| ; CHECK: lw      $26, [[R4:[0-9]+]]($sp)
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| ; CHECK: mthi    $26
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| ; CHECK: lw      $26, [[R3:[0-9]+]]($sp)
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| ; CHECK: mtlo    $26
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| ; CHECK: lw      $1, {{[0-9]+}}($sp)
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| ; CHECK: lw      $gp, {{[0-9]+}}($sp)
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| ; CHECK: lw      $ra, [[R5:[0-9]+]]($sp)
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| ; CHECK: lw      $8, {{[0-9]+}}($sp)
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| ; CHECK: lw      $9, {{[0-9]+}}($sp)
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| ; CHECK: lw      $10, {{[0-9]+}}($sp)
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| ; CHECK: lw      $11, {{[0-9]+}}($sp)
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| ; CHECK: lw      $12, {{[0-9]+}}($sp)
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| ; CHECK: lw      $13, {{[0-9]+}}($sp)
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| ; CHECK: lw      $14, {{[0-9]+}}($sp)
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| ; CHECK: lw      $15, {{[0-9]+}}($sp)
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| ; CHECK: lw      $24, {{[0-9]+}}($sp)
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| ; CHECK: lw      $25, {{[0-9]+}}($sp)
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| ; CHECK: lw      $2, {{[0-9]+}}($sp)
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| ; CHECK: lw      $3, {{[0-9]+}}($sp)
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| ; CHECK: lw      $4, {{[0-9]+}}($sp)
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| ; CHECK: lw      $5, {{[0-9]+}}($sp)
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| ; CHECK: lw      $6, {{[0-9]+}}($sp)
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| ; CHECK: lw      $7, {{[0-9]+}}($sp)
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, [[R2:[0-9]+]]($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, [[R1:[0-9]+]]($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|   ret void
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| }
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| 
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| declare void @write(...)
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| 
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| define void @isr_sw1() #2 {
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| ; CHECK-LABEL: isr_sw1:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 2
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| define void @isr_hw0() #3 {
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| ; CHECK-LABEL: isr_hw0:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 3
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| define void @isr_hw1() #4 {
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| ; CHECK-LABEL: isr_hw1:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 4
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| 
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| define void @isr_hw2() #5 {
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| ; CHECK-LABEL: isr_hw2:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 5
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| define void @isr_hw3() #6 {
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| ; CHECK-LABEL: isr_hw3:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 6
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| define void @isr_hw4() #7 {
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| ; CHECK-LABEL: isr_hw4:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 7
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| define void @isr_hw5() #8 {
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| ; CHECK-LABEL: isr_hw5:
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $zero, 8, 8
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| define void @isr_eic() #9 {
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| ; CHECK-LABEL: isr_eic:
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| ; CHECK: mfc0   $26, $13, 0
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| ; CHECK: ext    $26, $26, 10, 6
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| ; CHECK: mfc0   $27, $14, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: mfc0   $27, $12, 0
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| ; CHECK: sw     $27, {{[0-9]+}}($sp)
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| ; CHECK: ins    $27, $26, 10, 6
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| ; CHECK: ins    $27, $zero, 1, 4
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| ; CHECK: ins    $27, $zero, 29, 1
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| ; CHECK: mtc0   $27, $12, 0
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|   ret void
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| ; CHECK: di
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| ; CHECK: ehb
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $14, 0
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| ; CHECK: lw      $27, {{[0-9]+}}($sp)
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| ; CHECK: mtc0    $27, $12, 0
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| ; CHECK: eret
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|  }
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| 
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| attributes #0 = { "interrupt"="sw0" }
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| attributes #2 = { "interrupt"="sw1" }
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| attributes #3 = { "interrupt"="hw0" }
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| attributes #4 = { "interrupt"="hw1" }
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| attributes #5 = { "interrupt"="hw2" }
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| attributes #6 = { "interrupt"="hw3" }
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| attributes #7 = { "interrupt"="hw4" }
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| attributes #8 = { "interrupt"="hw5" }
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| attributes #9 = { "interrupt"="eic" }
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