177 lines
5.3 KiB
LLVM
177 lines
5.3 KiB
LLVM
; This test is designed to run twice, once with function attributes and once
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; with target attributes added on the command line.
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;
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; RUN: cat %s > %t.tgtattr
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; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
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; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \
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; RUN: -disable-block-placement < %t.tgtattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IC %s
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;
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; RUN: cat %s > %t.fnattr
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; RUN: echo 'attributes #0 = { nounwind "target-features"="+c" }' >> %t.fnattr
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; RUN: llc -mtriple=riscv32 -filetype=obj \
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; RUN: -disable-block-placement < %t.fnattr \
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; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c -M no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IC %s
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; This acts as a sanity check for the codegen instruction compression path,
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; verifying that the assembled file contains compressed instructions when
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; expected. Handling of the compressed ISA is implemented so the same
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; transformation patterns should be used whether compressing an input .s file or
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; compressing codegen output. This file contains sanity checks to ensure that is
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; working as expected. Particular care should be taken to test pseudo
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; instructions.
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; Note: TODOs in this file are only appropriate if they highlight a case where
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; a generated instruction that can be compressed by an existing pattern isn't.
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; It may be useful to have tests that indicate where better compression would be
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; possible if alternative codegen choices were made, but they belong in a
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; different test file.
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define i32 @simple_arith(i32 %a, i32 %b) #0 {
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; RV32IC-LABEL: <simple_arith>:
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; RV32IC: addi a2, a0, 1
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; RV32IC-NEXT: c.andi a2, 11
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; RV32IC-NEXT: c.slli a2, 7
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; RV32IC-NEXT: c.srai a1, 9
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; RV32IC-NEXT: c.add a1, a2
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; RV32IC-NEXT: sub a0, a1, a0
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; RV32IC-NEXT: c.jr ra
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%1 = add i32 %a, 1
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%2 = and i32 %1, 11
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%3 = shl i32 %2, 7
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%4 = ashr i32 %b, 9
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%5 = add i32 %3, %4
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%6 = sub i32 %5, %a
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ret i32 %6
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}
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define i32 @select(i32 %a, i32 *%b) #0 {
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; RV32IC-LABEL: <select>:
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; RV32IC: c.lw a2, 0(a1)
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; RV32IC-NEXT: c.beqz a2, 4
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: c.bnez a2, 4
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bltu a2, a0, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bgeu a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bltu a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bgeu a2, a0, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: blt a2, a0, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bge a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: blt a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a1, 0(a1)
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; RV32IC-NEXT: bge a1, a0, 6
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; RV32IC-NEXT: c.mv a0, a1
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; RV32IC-NEXT: c.jr ra
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%val1 = load volatile i32, i32* %b
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%tst1 = icmp eq i32 0, %val1
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%val2 = select i1 %tst1, i32 %a, i32 %val1
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%val3 = load volatile i32, i32* %b
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%tst2 = icmp ne i32 0, %val3
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%val4 = select i1 %tst2, i32 %val2, i32 %val3
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%val5 = load volatile i32, i32* %b
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%tst3 = icmp ugt i32 %val4, %val5
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%val6 = select i1 %tst3, i32 %val4, i32 %val5
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%val7 = load volatile i32, i32* %b
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%tst4 = icmp uge i32 %val6, %val7
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%val8 = select i1 %tst4, i32 %val6, i32 %val7
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%val9 = load volatile i32, i32* %b
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%tst5 = icmp ult i32 %val8, %val9
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%val10 = select i1 %tst5, i32 %val8, i32 %val9
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%val11 = load volatile i32, i32* %b
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%tst6 = icmp ule i32 %val10, %val11
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%val12 = select i1 %tst6, i32 %val10, i32 %val11
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%val13 = load volatile i32, i32* %b
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%tst7 = icmp sgt i32 %val12, %val13
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%val14 = select i1 %tst7, i32 %val12, i32 %val13
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%val15 = load volatile i32, i32* %b
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%tst8 = icmp sge i32 %val14, %val15
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%val16 = select i1 %tst8, i32 %val14, i32 %val15
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%val17 = load volatile i32, i32* %b
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%tst9 = icmp slt i32 %val16, %val17
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%val18 = select i1 %tst9, i32 %val16, i32 %val17
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%val19 = load volatile i32, i32* %b
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%tst10 = icmp sle i32 %val18, %val19
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%val20 = select i1 %tst10, i32 %val18, i32 %val19
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ret i32 %val20
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}
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define i32 @pos_tiny() #0 {
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; RV32IC-LABEL: <pos_tiny>:
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; RV32IC: c.li a0, 18
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; RV32IC-NEXT: c.jr ra
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ret i32 18
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}
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define i32 @pos_i32() #0 {
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; RV32IC-LABEL: <pos_i32>:
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; RV32IC: lui a0, 423811
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; RV32IC-NEXT: addi a0, a0, -1297
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; RV32IC-NEXT: c.jr ra
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ret i32 1735928559
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}
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define i32 @pos_i32_half_compressible() #0 {
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; RV32IC-LABEL: <pos_i32_half_compressible>:
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; RV32IC: lui a0, 423810
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; RV32IC-NEXT: c.addi a0, 28
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; RV32IC-NEXT: c.jr ra
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ret i32 1735925788
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}
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define i32 @neg_tiny() #0 {
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; RV32IC-LABEL: <neg_tiny>:
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; RV32IC: c.li a0, -19
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; RV32IC-NEXT: c.jr ra
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ret i32 -19
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}
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define i32 @neg_i32() #0 {
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; RV32IC-LABEL: <neg_i32>:
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; RV32IC: lui a0, 912092
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; RV32IC-NEXT: addi a0, a0, -273
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; RV32IC-NEXT: c.jr ra
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ret i32 -559038737
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}
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define i32 @pos_i32_hi20_only() #0 {
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; RV32IC-LABEL: <pos_i32_hi20_only>:
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; RV32IC: c.lui a0, 16
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; RV32IC-NEXT: c.jr ra
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ret i32 65536
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}
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define i32 @neg_i32_hi20_only() #0 {
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; RV32IC-LABEL: <neg_i32_hi20_only>:
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; RV32IC: c.lui a0, 1048560
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; RV32IC-NEXT: c.jr ra
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ret i32 -65536
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}
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