127 lines
3.9 KiB
LLVM
127 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
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; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
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; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
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declare void @abort()
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define void @eliminate_restore(i32 %n) nounwind {
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; RV32I-NOSW-LABEL: eliminate_restore:
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; RV32I-NOSW: # %bb.0:
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; RV32I-NOSW-NEXT: addi sp, sp, -16
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; RV32I-NOSW-NEXT: sw ra, 12(sp)
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; RV32I-NOSW-NEXT: addi a1, zero, 32
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; RV32I-NOSW-NEXT: bgeu a1, a0, .LBB0_2
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; RV32I-NOSW-NEXT: # %bb.1: # %if.end
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; RV32I-NOSW-NEXT: lw ra, 12(sp)
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; RV32I-NOSW-NEXT: addi sp, sp, 16
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; RV32I-NOSW-NEXT: ret
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; RV32I-NOSW-NEXT: .LBB0_2: # %if.then
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; RV32I-NOSW-NEXT: call abort
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;
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; RV32I-SW-LABEL: eliminate_restore:
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; RV32I-SW: # %bb.0:
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; RV32I-SW-NEXT: addi a1, zero, 32
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; RV32I-SW-NEXT: bgeu a1, a0, .LBB0_2
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; RV32I-SW-NEXT: # %bb.1: # %if.end
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; RV32I-SW-NEXT: ret
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; RV32I-SW-NEXT: .LBB0_2: # %if.then
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; RV32I-SW-NEXT: addi sp, sp, -16
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; RV32I-SW-NEXT: sw ra, 12(sp)
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; RV32I-SW-NEXT: call abort
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;
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; RV32I-SW-SR-LABEL: eliminate_restore:
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; RV32I-SW-SR: # %bb.0:
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; RV32I-SW-SR-NEXT: addi a1, zero, 32
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; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2
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; RV32I-SW-SR-NEXT: # %bb.1: # %if.end
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; RV32I-SW-SR-NEXT: ret
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; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then
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; RV32I-SW-SR-NEXT: call t0, __riscv_save_0
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; RV32I-SW-SR-NEXT: call abort
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%cmp = icmp ule i32 %n, 32
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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call void @abort()
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unreachable
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if.end:
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ret void
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}
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declare void @notdead(i8*)
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define void @conditional_alloca(i32 %n) nounwind {
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; RV32I-NOSW-LABEL: conditional_alloca:
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; RV32I-NOSW: # %bb.0:
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; RV32I-NOSW-NEXT: addi sp, sp, -16
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; RV32I-NOSW-NEXT: sw ra, 12(sp)
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; RV32I-NOSW-NEXT: sw s0, 8(sp)
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; RV32I-NOSW-NEXT: addi s0, sp, 16
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; RV32I-NOSW-NEXT: addi a1, zero, 32
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; RV32I-NOSW-NEXT: bltu a1, a0, .LBB1_2
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; RV32I-NOSW-NEXT: # %bb.1: # %if.then
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; RV32I-NOSW-NEXT: addi a0, a0, 15
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; RV32I-NOSW-NEXT: andi a0, a0, -16
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; RV32I-NOSW-NEXT: sub a0, sp, a0
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; RV32I-NOSW-NEXT: mv sp, a0
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; RV32I-NOSW-NEXT: call notdead
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; RV32I-NOSW-NEXT: .LBB1_2: # %if.end
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; RV32I-NOSW-NEXT: addi sp, s0, -16
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; RV32I-NOSW-NEXT: lw s0, 8(sp)
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; RV32I-NOSW-NEXT: lw ra, 12(sp)
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; RV32I-NOSW-NEXT: addi sp, sp, 16
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; RV32I-NOSW-NEXT: ret
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;
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; RV32I-SW-LABEL: conditional_alloca:
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; RV32I-SW: # %bb.0:
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; RV32I-SW-NEXT: addi a1, zero, 32
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; RV32I-SW-NEXT: bltu a1, a0, .LBB1_2
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; RV32I-SW-NEXT: # %bb.1: # %if.then
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; RV32I-SW-NEXT: addi sp, sp, -16
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; RV32I-SW-NEXT: sw ra, 12(sp)
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; RV32I-SW-NEXT: sw s0, 8(sp)
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; RV32I-SW-NEXT: addi s0, sp, 16
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; RV32I-SW-NEXT: addi a0, a0, 15
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; RV32I-SW-NEXT: andi a0, a0, -16
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; RV32I-SW-NEXT: sub a0, sp, a0
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; RV32I-SW-NEXT: mv sp, a0
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; RV32I-SW-NEXT: call notdead
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; RV32I-SW-NEXT: addi sp, s0, -16
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; RV32I-SW-NEXT: lw s0, 8(sp)
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; RV32I-SW-NEXT: lw ra, 12(sp)
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; RV32I-SW-NEXT: addi sp, sp, 16
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; RV32I-SW-NEXT: .LBB1_2: # %if.end
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; RV32I-SW-NEXT: ret
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;
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; RV32I-SW-SR-LABEL: conditional_alloca:
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; RV32I-SW-SR: # %bb.0:
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; RV32I-SW-SR-NEXT: addi a1, zero, 32
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; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2
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; RV32I-SW-SR-NEXT: # %bb.1: # %if.then
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; RV32I-SW-SR-NEXT: call t0, __riscv_save_1
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; RV32I-SW-SR-NEXT: addi s0, sp, 16
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; RV32I-SW-SR-NEXT: addi a0, a0, 15
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; RV32I-SW-SR-NEXT: andi a0, a0, -16
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; RV32I-SW-SR-NEXT: sub a0, sp, a0
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; RV32I-SW-SR-NEXT: mv sp, a0
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; RV32I-SW-SR-NEXT: call notdead
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; RV32I-SW-SR-NEXT: addi sp, s0, -16
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; RV32I-SW-SR-NEXT: tail __riscv_restore_1
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; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end
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; RV32I-SW-SR-NEXT: ret
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%cmp = icmp ule i32 %n, 32
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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%addr = alloca i8, i32 %n
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call void @notdead(i8* %addr)
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br label %if.end
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if.end:
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ret void
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}
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