296 lines
7.6 KiB
LLVM
296 lines
7.6 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that bitcasts between vector types are lowered to zero instructions
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; CHECK-LABEL: v16i8_to_v16i8:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {
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%res = bitcast <16 x i8> %v to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: v16i8_to_v8i16:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {
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%res = bitcast <16 x i8> %v to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: v16i8_to_v4i32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
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%res = bitcast <16 x i8> %v to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: v16i8_to_v2i64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
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%res = bitcast <16 x i8> %v to <2 x i64>
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ret <2 x i64> %res
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}
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; CHECK-LABEL: v16i8_to_v4f32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
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%res = bitcast <16 x i8> %v to <4 x float>
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ret <4 x float> %res
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}
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; CHECK-LABEL: v16i8_to_v2f64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
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%res = bitcast <16 x i8> %v to <2 x double>
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ret <2 x double> %res
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}
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; CHECK-LABEL: v8i16_to_v16i8:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {
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%res = bitcast <8 x i16> %v to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: v8i16_to_v8i16:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {
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%res = bitcast <8 x i16> %v to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: v8i16_to_v4i32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
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%res = bitcast <8 x i16> %v to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: v8i16_to_v2i64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
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%res = bitcast <8 x i16> %v to <2 x i64>
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ret <2 x i64> %res
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}
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; CHECK-LABEL: v8i16_to_v4f32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
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%res = bitcast <8 x i16> %v to <4 x float>
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ret <4 x float> %res
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}
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; CHECK-LABEL: v8i16_to_v2f64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
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%res = bitcast <8 x i16> %v to <2 x double>
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ret <2 x double> %res
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}
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; CHECK-LABEL: v4i32_to_v16i8:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {
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%res = bitcast <4 x i32> %v to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: v4i32_to_v8i16:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {
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%res = bitcast <4 x i32> %v to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: v4i32_to_v4i32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
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%res = bitcast <4 x i32> %v to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: v4i32_to_v2i64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
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%res = bitcast <4 x i32> %v to <2 x i64>
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ret <2 x i64> %res
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}
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; CHECK-LABEL: v4i32_to_v4f32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
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%res = bitcast <4 x i32> %v to <4 x float>
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ret <4 x float> %res
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}
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; CHECK-LABEL: v4i32_to_v2f64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
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%res = bitcast <4 x i32> %v to <2 x double>
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ret <2 x double> %res
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}
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; CHECK-LABEL: v2i64_to_v16i8:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
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%res = bitcast <2 x i64> %v to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: v2i64_to_v8i16:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
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%res = bitcast <2 x i64> %v to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: v2i64_to_v4i32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
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%res = bitcast <2 x i64> %v to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: v2i64_to_v2i64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
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%res = bitcast <2 x i64> %v to <2 x i64>
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ret <2 x i64> %res
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}
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; CHECK-LABEL: v2i64_to_v4f32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
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%res = bitcast <2 x i64> %v to <4 x float>
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ret <4 x float> %res
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}
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; CHECK-LABEL: v2i64_to_v2f64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
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%res = bitcast <2 x i64> %v to <2 x double>
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ret <2 x double> %res
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}
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; CHECK-LABEL: v4f32_to_v16i8:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {
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%res = bitcast <4 x float> %v to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: v4f32_to_v8i16:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {
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%res = bitcast <4 x float> %v to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: v4f32_to_v4i32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
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%res = bitcast <4 x float> %v to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: v4f32_to_v2i64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
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%res = bitcast <4 x float> %v to <2 x i64>
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ret <2 x i64> %res
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}
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; CHECK-LABEL: v4f32_to_v4f32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
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%res = bitcast <4 x float> %v to <4 x float>
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ret <4 x float> %res
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}
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; CHECK-LABEL: v4f32_to_v2f64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
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%res = bitcast <4 x float> %v to <2 x double>
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ret <2 x double> %res
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}
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; CHECK-LABEL: v2f64_to_v16i8:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
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%res = bitcast <2 x double> %v to <16 x i8>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: v2f64_to_v8i16:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
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%res = bitcast <2 x double> %v to <8 x i16>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: v2f64_to_v4i32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
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%res = bitcast <2 x double> %v to <4 x i32>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: v2f64_to_v2i64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
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%res = bitcast <2 x double> %v to <2 x i64>
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ret <2 x i64> %res
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}
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; CHECK-LABEL: v2f64_to_v4f32:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
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%res = bitcast <2 x double> %v to <4 x float>
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ret <4 x float> %res
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}
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; CHECK-LABEL: v2f64_to_v2f64:
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; NO-SIMD128-NOT: return $0
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; SIMD128: return $0
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define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
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%res = bitcast <2 x double> %v to <2 x double>
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ret <2 x double> %res
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}
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