28 lines
1.2 KiB
LLVM
28 lines
1.2 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=simd128 | FileCheck %s --check-prefixes CHECK
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; Test that BUILD_PAIR dag nodes are correctly lowered.
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; This code produces a selection DAG like the following:
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; t0: ch = EntryToken
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; t3: v4i32,ch = load<(load 16 from `<4 x i32>* undef`)> t0, undef:i32, undef:i32
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; t30: i32 = extract_vector_elt t3, Constant:i32<2>
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; t28: i32 = extract_vector_elt t3, Constant:i32<3>
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; t24: i64 = build_pair t30, t28
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; t8: ch = store<(store 8 into `i64* undef`, align 1)> t3:1, t24, undef:i32, undef:i32
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; t9: ch = WebAssemblyISD::RETURN t8
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; CHECK: i64x2.extract_lane
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; CHECK-NEXT: i64.store
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define void @build_pair_i32s() {
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entry:
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%0 = load <4 x i32>, <4 x i32>* undef, align 16
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%shuffle.i184 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%bc357 = bitcast <4 x i32> %shuffle.i184 to <2 x i64>
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%1 = extractelement <2 x i64> %bc357, i32 0
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store i64 %1, i64* undef, align 1
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ret void
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}
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