151 lines
7.2 KiB
LLVM
151 lines
7.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-interchange -verify-loop-lcssa -S %s | FileCheck %s
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; Tests for PR43797.
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@wdtdr = external dso_local global [5 x [5 x double]], align 16
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define void @test1() {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[INNER_HEADER_PREHEADER:%.*]]
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; CHECK: outer.header.preheader:
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: [[OUTER_IDX:%.*]] = phi i64 [ [[OUTER_IDX_INC:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [5 x double]], [5 x [5 x double]]* @wdtdr, i64 0, i64 0, i64 [[OUTER_IDX]]
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; CHECK-NEXT: br label [[INNER_HEADER_SPLIT:%.*]]
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; CHECK: inner.header.preheader:
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; CHECK-NEXT: br label [[INNER_HEADER:%.*]]
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; CHECK: inner.header:
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; CHECK-NEXT: [[INNER_IDX:%.*]] = phi i64 [ [[TMP3:%.*]], [[INNER_LATCH_SPLIT:%.*]] ], [ 0, [[INNER_HEADER_PREHEADER]] ]
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; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
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; CHECK: inner.header.split:
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; CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[ARRAYIDX8]], align 8
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; CHECK-NEXT: store double undef, double* [[ARRAYIDX8]], align 8
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; CHECK-NEXT: br label [[INNER_LATCH:%.*]]
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; CHECK: inner.latch:
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; CHECK-NEXT: [[INNER_IDX_INC:%.*]] = add nsw i64 [[INNER_IDX]], 1
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; CHECK-NEXT: br label [[INNER_EXIT:%.*]]
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; CHECK: inner.latch.split:
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; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ [[OUTER_V:%.*]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ [[OUTER_IDX_INC]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: [[TMP3]] = add nsw i64 [[INNER_IDX]], 1
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; CHECK-NEXT: br i1 false, label [[INNER_HEADER]], label [[OUTER_EXIT:%.*]]
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; CHECK: inner.exit:
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; CHECK-NEXT: [[OUTER_V]] = add nsw i64 [[OUTER_IDX]], 1
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; CHECK-NEXT: br label [[OUTER_LATCH]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[OUTER_IDX_INC]] = add nsw i64 [[OUTER_IDX]], 1
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; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[INNER_LATCH_SPLIT]]
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; CHECK: outer.exit:
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; CHECK-NEXT: [[EXIT1_LCSSA:%.*]] = phi i64 [ [[TMP1]], [[INNER_LATCH_SPLIT]] ]
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; CHECK-NEXT: [[EXIT2_LCSSA:%.*]] = phi i64 [ [[TMP2]], [[INNER_LATCH_SPLIT]] ]
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; CHECK-NEXT: ret void
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;
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entry:
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br label %outer.header
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outer.header: ; preds = %for.inc27, %entry
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%outer.idx = phi i64 [ 0, %entry ], [ %outer.idx.inc, %outer.latch ]
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%arrayidx8 = getelementptr inbounds [5 x [5 x double]], [5 x [5 x double]]* @wdtdr, i64 0, i64 0, i64 %outer.idx
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br label %inner.header
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inner.header: ; preds = %for.inc, %for.body
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%inner.idx = phi i64 [ 0, %outer.header ], [ %inner.idx.inc, %inner.latch]
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%0 = load double, double* %arrayidx8, align 8
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store double undef, double* %arrayidx8, align 8
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br label %inner.latch
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inner.latch: ; preds = %for.body6
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%inner.idx.inc = add nsw i64 %inner.idx, 1
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br i1 undef, label %inner.header, label %inner.exit
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inner.exit: ; preds = %for.inc
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%outer.v = add nsw i64 %outer.idx, 1
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br label %outer.latch
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outer.latch: ; preds = %for.end
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%outer.idx.inc = add nsw i64 %outer.idx, 1
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br i1 undef, label %outer.header, label %outer.exit
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outer.exit: ; preds = %for.inc27
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%exit1.lcssa = phi i64 [ %outer.v, %outer.latch ]
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%exit2.lcssa = phi i64 [ %outer.idx.inc, %outer.latch ]
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ret void
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}
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define void @test2(i1 %cond) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[COND:%.*]], label [[INNER_HEADER_PREHEADER:%.*]], label [[OUTER_EXIT:%.*]]
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; CHECK: outer.header.preheader:
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; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
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; CHECK: outer.header:
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; CHECK-NEXT: [[OUTER_IDX:%.*]] = phi i64 [ [[OUTER_IDX_INC:%.*]], [[OUTER_LATCH:%.*]] ], [ 0, [[OUTER_HEADER_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x [5 x double]], [5 x [5 x double]]* @wdtdr, i64 0, i64 0, i64 [[OUTER_IDX]]
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; CHECK-NEXT: br label [[INNER_HEADER_SPLIT:%.*]]
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; CHECK: inner.header.preheader:
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; CHECK-NEXT: br label [[INNER_HEADER:%.*]]
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; CHECK: inner.header:
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; CHECK-NEXT: [[INNER_IDX:%.*]] = phi i64 [ [[TMP3:%.*]], [[INNER_LATCH_SPLIT:%.*]] ], [ 0, [[INNER_HEADER_PREHEADER]] ]
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; CHECK-NEXT: br label [[OUTER_HEADER_PREHEADER]]
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; CHECK: inner.header.split:
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; CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[ARRAYIDX8]], align 8
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; CHECK-NEXT: store double undef, double* [[ARRAYIDX8]], align 8
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; CHECK-NEXT: br label [[INNER_LATCH:%.*]]
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; CHECK: inner.latch:
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; CHECK-NEXT: [[INNER_IDX_INC:%.*]] = add nsw i64 [[INNER_IDX]], 1
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; CHECK-NEXT: br label [[INNER_EXIT:%.*]]
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; CHECK: inner.latch.split:
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; CHECK-NEXT: [[TMP1:%.*]] = phi i64 [ [[OUTER_IDX_INC]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i64 [ [[OUTER_V:%.*]], [[OUTER_LATCH]] ]
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; CHECK-NEXT: [[TMP3]] = add nsw i64 [[INNER_IDX]], 1
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; CHECK-NEXT: br i1 false, label [[INNER_HEADER]], label [[OUTER_EXIT_LOOPEXIT:%.*]]
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; CHECK: inner.exit:
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; CHECK-NEXT: [[OUTER_V]] = add nsw i64 [[OUTER_IDX]], 1
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; CHECK-NEXT: br label [[OUTER_LATCH]]
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; CHECK: outer.latch:
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; CHECK-NEXT: [[OUTER_IDX_INC]] = add nsw i64 [[OUTER_IDX]], 1
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; CHECK-NEXT: br i1 false, label [[OUTER_HEADER]], label [[INNER_LATCH_SPLIT]]
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; CHECK: outer.exit.loopexit:
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; CHECK-NEXT: [[OUTER_IDX_INC_LCSSA:%.*]] = phi i64 [ [[TMP1]], [[INNER_LATCH_SPLIT]] ]
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; CHECK-NEXT: [[OUTER_V_LCSSA:%.*]] = phi i64 [ [[TMP2]], [[INNER_LATCH_SPLIT]] ]
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; CHECK-NEXT: br label [[OUTER_EXIT]]
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; CHECK: outer.exit:
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; CHECK-NEXT: [[EXIT1_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_V_LCSSA]], [[OUTER_EXIT_LOOPEXIT]] ]
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; CHECK-NEXT: [[EXIT2_LCSSA:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[OUTER_IDX_INC_LCSSA]], [[OUTER_EXIT_LOOPEXIT]] ]
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %cond, label %outer.header, label %outer.exit
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outer.header: ; preds = %for.inc27, %entry
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%outer.idx = phi i64 [ 0, %entry ], [ %outer.idx.inc, %outer.latch ]
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%arrayidx8 = getelementptr inbounds [5 x [5 x double]], [5 x [5 x double]]* @wdtdr, i64 0, i64 0, i64 %outer.idx
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br label %inner.header
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inner.header: ; preds = %for.inc, %for.body
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%inner.idx = phi i64 [ 0, %outer.header ], [ %inner.idx.inc, %inner.latch]
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%0 = load double, double* %arrayidx8, align 8
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store double undef, double* %arrayidx8, align 8
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br label %inner.latch
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inner.latch: ; preds = %for.body6
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%inner.idx.inc = add nsw i64 %inner.idx , 1
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br i1 undef, label %inner.header, label %inner.exit
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inner.exit: ; preds = %for.inc
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%outer.v = add nsw i64 %outer.idx, 1
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br label %outer.latch
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outer.latch: ; preds = %for.end
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%outer.idx.inc = add nsw i64 %outer.idx, 1
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br i1 undef, label %outer.header, label %outer.exit
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outer.exit: ; preds = %for.inc27
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%exit1.lcssa = phi i64 [ 0, %entry ], [ %outer.v, %outer.latch ]
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%exit2.lcssa = phi i64 [ 0, %entry ], [ %outer.idx.inc, %outer.latch ]
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ret void
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}
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