1958 lines
73 KiB
ReStructuredText
1958 lines
73 KiB
ReStructuredText
======================================
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Syntax of AMDGPU Instruction Modifiers
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======================================
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.. contents::
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:local:
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Conventions
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===========
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The following notation is used throughout this document:
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=================== =============================================================
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Notation Description
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=================== =============================================================
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{0..N} Any integer value in the range from 0 to N (inclusive).
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<x> Syntax and meaning of *x* is explained elsewhere.
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=================== =============================================================
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.. _amdgpu_syn_modifiers:
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Modifiers
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=========
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DS Modifiers
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------------
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.. _amdgpu_synid_ds_offset80:
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offset0
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~~~~~~~
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Specifies first 8-bit offset, in bytes. The default value is 0.
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Used with DS instructions that expect two addresses.
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=================== ====================================================================
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Syntax Description
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=================== ====================================================================
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offset0:{0..0xFF} Specifies an unsigned 8-bit offset as a positive
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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=================== ====================================================================
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Examples:
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.. parsed-literal::
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offset0:0xff
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offset0:2-x
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offset0:-x-y
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.. _amdgpu_synid_ds_offset81:
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offset1
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~~~~~~~
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Specifies second 8-bit offset, in bytes. The default value is 0.
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Used with DS instructions that expect two addresses.
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=================== ====================================================================
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Syntax Description
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=================== ====================================================================
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offset1:{0..0xFF} Specifies an unsigned 8-bit offset as a positive
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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=================== ====================================================================
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Examples:
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.. parsed-literal::
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offset1:0xff
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offset1:2-x
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offset1:-x-y
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.. _amdgpu_synid_ds_offset16:
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offset
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~~~~~~
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Specifies a 16-bit offset, in bytes. The default value is 0.
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Used with DS instructions that expect a single address.
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==================== ====================================================================
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Syntax Description
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==================== ====================================================================
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offset:{0..0xFFFF} Specifies an unsigned 16-bit offset as a positive
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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==================== ====================================================================
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Examples:
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.. parsed-literal::
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offset:65535
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offset:0xffff
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offset:-x-y
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.. _amdgpu_synid_sw_offset16:
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swizzle pattern
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~~~~~~~~~~~~~~~
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This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
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It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.
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See AMD documentation for more information.
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======================================================= ===========================================================
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Syntax Description
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======================================================= ===========================================================
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offset:{0..0xFFFF} Specifies a 16-bit swizzle pattern.
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offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern
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Each number is a lane *id*.
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offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern.
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The pattern converts a 5-bit lane *id* to another
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lane *id* with which the lane interacts.
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*mask* is a 5 character sequence which
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specifies how to transform the bits of the
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lane *id*.
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The following characters are allowed:
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* "0" - set bit to 0.
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* "1" - set bit to 1.
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* "p" - preserve bit.
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* "i" - inverse bit.
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offset:swizzle(BROADCAST,{2..32},{0..N}) Specifies a broadcast mode.
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Broadcasts the value of any particular lane to
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all lanes in its group.
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The first numeric parameter is a group
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size and must be equal to 2, 4, 8, 16 or 32.
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The second numeric parameter is an index of the
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lane being broadcasted.
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The index must not exceed group size.
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offset:swizzle(SWAP,{1..16}) Specifies a swap mode.
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Swaps the neighboring groups of
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1, 2, 4, 8 or 16 lanes.
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offset:swizzle(REVERSE,{2..32}) Specifies a reverse mode.
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Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.
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======================================================= ===========================================================
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Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
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:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Examples:
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.. parsed-literal::
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offset:255
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offset:0xffff
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offset:swizzle(QUAD_PERM, 0, 1, 2, 3)
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offset:swizzle(BITMASK_PERM, "01pi0")
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offset:swizzle(BROADCAST, 2, 0)
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offset:swizzle(SWAP, 8)
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offset:swizzle(REVERSE, 30 + 2)
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.. _amdgpu_synid_gds:
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gds
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~~~
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Specifies whether to use GDS or LDS memory (LDS is the default).
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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gds Use GDS memory.
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======================================== ================================================
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EXP Modifiers
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-------------
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.. _amdgpu_synid_done:
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done
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~~~~
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Specifies if this is the last export from the shader to the target. By default,
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*exp* instruction does not finish an export sequence.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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done Indicates the last export operation.
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======================================== ================================================
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.. _amdgpu_synid_compr:
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compr
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~~~~~
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Indicates if the data are compressed (data are not compressed by default).
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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compr Data are compressed.
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======================================== ================================================
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.. _amdgpu_synid_vm:
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vm
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~~
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Specifies valid mask flag state (off by default).
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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vm Set valid mask flag.
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======================================== ================================================
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FLAT Modifiers
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--------------
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.. _amdgpu_synid_flat_offset12:
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offset12
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~~~~~~~~
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Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
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Cannot be used with *global/scratch* opcodes. GFX9 only.
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================= ====================================================================
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Syntax Description
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================= ====================================================================
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offset:{0..4095} Specifies a 12-bit unsigned offset as a positive
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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================= ====================================================================
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Examples:
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.. parsed-literal::
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offset:4095
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offset:x-0xff
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.. _amdgpu_synid_flat_offset13s:
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offset13s
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~~~~~~~~~
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Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.
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Can be used with *global/scratch* opcodes only. GFX9 only.
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===================== ====================================================================
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Syntax Description
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===================== ====================================================================
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offset:{-4096..4095} Specifies a 13-bit signed offset as an
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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===================== ====================================================================
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Examples:
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.. parsed-literal::
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offset:-4000
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offset:0x10
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offset:-x
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.. _amdgpu_synid_flat_offset12s:
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offset12s
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~~~~~~~~~
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Specifies an immediate signed 12-bit offset, in bytes. The default value is 0.
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Can be used with *global/scratch* opcodes only.
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GFX10 only.
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===================== ====================================================================
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Syntax Description
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===================== ====================================================================
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offset:{-2048..2047} Specifies a 12-bit signed offset as an
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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===================== ====================================================================
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Examples:
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.. parsed-literal::
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offset:-2000
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offset:0x10
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offset:-x+y
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.. _amdgpu_synid_flat_offset11:
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offset11
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~~~~~~~~
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Specifies an immediate unsigned 11-bit offset, in bytes. The default value is 0.
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Cannot be used with *global/scratch* opcodes.
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GFX10 only.
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================= ====================================================================
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Syntax Description
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================= ====================================================================
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offset:{0..2047} Specifies an 11-bit unsigned offset as a positive
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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================= ====================================================================
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Examples:
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.. parsed-literal::
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offset:2047
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offset:x+0xff
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dlc
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~~~
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See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
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glc
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~~~
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See a description :ref:`here<amdgpu_synid_glc>`.
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lds
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~~~
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See a description :ref:`here<amdgpu_synid_lds>`. GFX10 only.
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slc
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~~~
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See a description :ref:`here<amdgpu_synid_slc>`.
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tfe
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~~~
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See a description :ref:`here<amdgpu_synid_tfe>`.
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nv
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~~
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See a description :ref:`here<amdgpu_synid_nv>`.
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MIMG Modifiers
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--------------
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.. _amdgpu_synid_dmask:
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dmask
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~~~~~
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Specifies which channels (image components) are used by the operation. By default, no channels
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are used.
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=============== ====================================================================
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Syntax Description
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=============== ====================================================================
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dmask:{0..15} Specifies image channels as a positive
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:ref:`integer number <amdgpu_synid_integer_number>`
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or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
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Each bit corresponds to one of 4 image components (RGBA).
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If the specified bit value is 0, the component is not used,
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value 1 means that the component is used.
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=============== ====================================================================
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This modifier has some limitations depending on instruction kind:
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=================================================== ========================
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Instruction Kind Valid dmask Values
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=================================================== ========================
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32-bit atomic *cmpswap* 0x3
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32-bit atomic instructions except for *cmpswap* 0x1
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64-bit atomic *cmpswap* 0xF
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64-bit atomic instructions except for *cmpswap* 0x3
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*gather4* 0x1, 0x2, 0x4, 0x8
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Other instructions any value
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=================================================== ========================
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Examples:
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.. parsed-literal::
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dmask:0xf
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dmask:0b1111
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dmask:x|y|z
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.. _amdgpu_synid_unorm:
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unorm
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~~~~~
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Specifies whether the address is normalized or not (the address is normalized by default).
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======================== ========================================
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Syntax Description
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======================== ========================================
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unorm Force the address to be unnormalized.
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======================== ========================================
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glc
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~~~
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See a description :ref:`here<amdgpu_synid_glc>`.
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slc
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~~~
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See a description :ref:`here<amdgpu_synid_slc>`.
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.. _amdgpu_synid_r128:
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r128
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~~~~
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Specifies texture resource size. The default size is 256 bits.
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GFX7, GFX8 and GFX10 only.
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=================== ================================================
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Syntax Description
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=================== ================================================
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r128 Specifies 128 bits texture resource size.
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=================== ================================================
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.. WARNING:: Using this modifier should decrease *rsrc* operand size from 8 to 4 dwords, but assembler does not currently support this feature.
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tfe
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~~~
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See a description :ref:`here<amdgpu_synid_tfe>`.
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.. _amdgpu_synid_lwe:
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lwe
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~~~
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Specifies LOD warning status (LOD warning is disabled by default).
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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lwe Enables LOD warning.
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======================================== ================================================
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.. _amdgpu_synid_da:
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da
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~~
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Specifies if an array index must be sent to TA. By default, array index is not sent.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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da Send an array-index to TA.
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======================================== ================================================
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.. _amdgpu_synid_d16:
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d16
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~~~
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Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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d16 Enables 16-bits data mode.
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On loads, convert data in memory to 16-bit
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format before storing it in VGPRs.
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For stores, convert 16-bit data in VGPRs to
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32 bits before going to memory.
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Note that GFX8.0 does not support data packing.
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Each 16-bit data element occupies 1 VGPR.
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GFX8.1, GFX9 and GFX10 support data packing.
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Each pair of 16-bit data elements
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occupies 1 VGPR.
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======================================== ================================================
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.. _amdgpu_synid_a16:
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a16
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~~~
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Specifies size of image address components: 16 or 32 bits (32 bits by default).
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GFX9 and GFX10 only.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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a16 Enables 16-bits image address components.
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======================================== ================================================
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.. _amdgpu_synid_dim:
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dim
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~~~
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Specifies surface dimension. This is a mandatory modifier. There is no default value.
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GFX10 only.
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=============================== =========================================================
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Syntax Description
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=============================== =========================================================
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dim:1D One-dimensional image.
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dim:2D Two-dimensional image.
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dim:3D Three-dimensional image.
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dim:CUBE Cubemap array.
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dim:1D_ARRAY One-dimensional image array.
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dim:2D_ARRAY Two-dimensional image array.
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dim:2D_MSAA Two-dimensional multi-sample auto-aliasing image.
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dim:2D_MSAA_ARRAY Two-dimensional multi-sample auto-aliasing image array.
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=============================== =========================================================
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The following table defines an alternative syntax which is supported
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for compatibility with SP3 assembler:
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=============================== =========================================================
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Syntax Description
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=============================== =========================================================
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dim:SQ_RSRC_IMG_1D One-dimensional image.
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dim:SQ_RSRC_IMG_2D Two-dimensional image.
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dim:SQ_RSRC_IMG_3D Three-dimensional image.
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dim:SQ_RSRC_IMG_CUBE Cubemap array.
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dim:SQ_RSRC_IMG_1D_ARRAY One-dimensional image array.
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dim:SQ_RSRC_IMG_2D_ARRAY Two-dimensional image array.
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dim:SQ_RSRC_IMG_2D_MSAA Two-dimensional multi-sample auto-aliasing image.
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dim:SQ_RSRC_IMG_2D_MSAA_ARRAY Two-dimensional multi-sample auto-aliasing image array.
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=============================== =========================================================
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dlc
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~~~
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See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
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Miscellaneous Modifiers
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-----------------------
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.. _amdgpu_synid_dlc:
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dlc
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~~~
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Controls device level cache policy for memory operations. Used for synchronization.
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When specified, forces operation to bypass device level cache making the operation device
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level coherent. By default, instructions use device level cache.
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GFX10 only.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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dlc Bypass device level cache.
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======================================== ================================================
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.. _amdgpu_synid_glc:
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glc
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~~~
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This modifier has different meaning for loads, stores, and atomic operations.
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The default value is off (0).
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See AMD documentation for details.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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glc Set glc bit to 1.
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======================================== ================================================
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.. _amdgpu_synid_lds:
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lds
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~~~
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Specifies where to store the result: VGPRs or LDS (VGPRs by default).
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======================================== ===========================
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Syntax Description
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======================================== ===========================
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lds Store result in LDS.
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======================================== ===========================
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.. _amdgpu_synid_nv:
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nv
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~~
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Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.
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GFX9 only.
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======================================== ================================================
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Syntax Description
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======================================== ================================================
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nv Indicates that instruction operates on
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non-volatile memory.
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======================================== ================================================
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.. _amdgpu_synid_slc:
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slc
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~~~
|
|
|
|
Specifies cache policy. The default value is off (0).
|
|
|
|
See AMD documentation for details.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
slc Set slc bit to 1.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_tfe:
|
|
|
|
tfe
|
|
~~~
|
|
|
|
Controls access to partially resident textures. The default value is off (0).
|
|
|
|
See AMD documentation for details.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
tfe Set tfe bit to 1.
|
|
======================================== ================================================
|
|
|
|
MUBUF/MTBUF Modifiers
|
|
---------------------
|
|
|
|
.. _amdgpu_synid_idxen:
|
|
|
|
idxen
|
|
~~~~~
|
|
|
|
Specifies whether address components include an index. By default, no components are used.
|
|
|
|
Can be used together with :ref:`offen<amdgpu_synid_offen>`.
|
|
|
|
Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
idxen Address components include an index.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_offen:
|
|
|
|
offen
|
|
~~~~~
|
|
|
|
Specifies whether address components include an offset. By default, no components are used.
|
|
|
|
Can be used together with :ref:`idxen<amdgpu_synid_idxen>`.
|
|
|
|
Cannot be used with :ref:`addr64<amdgpu_synid_addr64>`.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
offen Address components include an offset.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_addr64:
|
|
|
|
addr64
|
|
~~~~~~
|
|
|
|
Specifies whether a 64-bit address is used. By default, no address is used.
|
|
|
|
GFX7 only. Cannot be used with :ref:`offen<amdgpu_synid_offen>` and
|
|
:ref:`idxen<amdgpu_synid_idxen>` modifiers.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
addr64 A 64-bit address is used.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_buf_offset12:
|
|
|
|
offset12
|
|
~~~~~~~~
|
|
|
|
Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.
|
|
|
|
================== ====================================================================
|
|
Syntax Description
|
|
================== ====================================================================
|
|
offset:{0..0xFFF} Specifies a 12-bit unsigned offset as a positive
|
|
:ref:`integer number <amdgpu_synid_integer_number>`
|
|
or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
================== ====================================================================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
offset:x+y
|
|
offset:0x10
|
|
|
|
glc
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_glc>`.
|
|
|
|
slc
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_slc>`.
|
|
|
|
lds
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_lds>`.
|
|
|
|
dlc
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
|
|
|
|
tfe
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_tfe>`.
|
|
|
|
.. _amdgpu_synid_fmt:
|
|
|
|
fmt
|
|
~~~
|
|
|
|
Specifies data and numeric formats used by the operation.
|
|
The default numeric format is BUF_NUM_FORMAT_UNORM.
|
|
The default data format is BUF_DATA_FORMAT_8.
|
|
|
|
========================================= ===============================================================
|
|
Syntax Description
|
|
========================================= ===============================================================
|
|
format:{0..127} Use format specified as either an
|
|
:ref:`integer number<amdgpu_synid_integer_number>` or an
|
|
:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
format:[<data format>] Use the specified data format and
|
|
default numeric format.
|
|
format:[<numeric format>] Use the specified numeric format and
|
|
default data format.
|
|
format:[<data format>, <numeric format>] Use the specified data and numeric formats.
|
|
format:[<numeric format>, <data format>] Use the specified data and numeric formats.
|
|
========================================= ===============================================================
|
|
|
|
.. _amdgpu_synid_format_data:
|
|
|
|
Supported data formats are defined in the following table:
|
|
|
|
========================================= ===============================
|
|
Syntax Note
|
|
========================================= ===============================
|
|
BUF_DATA_FORMAT_INVALID
|
|
BUF_DATA_FORMAT_8 Default value.
|
|
BUF_DATA_FORMAT_16
|
|
BUF_DATA_FORMAT_8_8
|
|
BUF_DATA_FORMAT_32
|
|
BUF_DATA_FORMAT_16_16
|
|
BUF_DATA_FORMAT_10_11_11
|
|
BUF_DATA_FORMAT_11_11_10
|
|
BUF_DATA_FORMAT_10_10_10_2
|
|
BUF_DATA_FORMAT_2_10_10_10
|
|
BUF_DATA_FORMAT_8_8_8_8
|
|
BUF_DATA_FORMAT_32_32
|
|
BUF_DATA_FORMAT_16_16_16_16
|
|
BUF_DATA_FORMAT_32_32_32
|
|
BUF_DATA_FORMAT_32_32_32_32
|
|
BUF_DATA_FORMAT_RESERVED_15
|
|
========================================= ===============================
|
|
|
|
.. _amdgpu_synid_format_num:
|
|
|
|
Supported numeric formats are defined below:
|
|
|
|
========================================= ===============================
|
|
Syntax Note
|
|
========================================= ===============================
|
|
BUF_NUM_FORMAT_UNORM Default value.
|
|
BUF_NUM_FORMAT_SNORM
|
|
BUF_NUM_FORMAT_USCALED
|
|
BUF_NUM_FORMAT_SSCALED
|
|
BUF_NUM_FORMAT_UINT
|
|
BUF_NUM_FORMAT_SINT
|
|
BUF_NUM_FORMAT_SNORM_OGL GFX7 only.
|
|
BUF_NUM_FORMAT_RESERVED_6 GFX8 and GFX9 only.
|
|
BUF_NUM_FORMAT_FLOAT
|
|
========================================= ===============================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
format:0
|
|
format:127
|
|
format:[BUF_DATA_FORMAT_16]
|
|
format:[BUF_DATA_FORMAT_16,BUF_NUM_FORMAT_SSCALED]
|
|
format:[BUF_NUM_FORMAT_FLOAT]
|
|
|
|
.. _amdgpu_synid_ufmt:
|
|
|
|
ufmt
|
|
~~~~
|
|
|
|
Specifies a unified format used by the operation.
|
|
The default format is BUF_FMT_8_UNORM.
|
|
GFX10 only.
|
|
|
|
========================================= ===============================================================
|
|
Syntax Description
|
|
========================================= ===============================================================
|
|
format:{0..127} Use unified format specified as either an
|
|
:ref:`integer number<amdgpu_synid_integer_number>` or an
|
|
:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
Note that unified format numbers are not compatible with
|
|
format numbers used for pre-GFX10 ISA.
|
|
format:[<unified format>] Use the specified unified format.
|
|
========================================= ===============================================================
|
|
|
|
Unified format is a replacement for :ref:`data<amdgpu_synid_format_data>`
|
|
and :ref:`numeric<amdgpu_synid_format_num>` formats. For compatibility with older ISA,
|
|
:ref:`syntax with data and numeric formats<amdgpu_synid_fmt>` is still accepted
|
|
provided that the combination of formats can be mapped to a unified format.
|
|
|
|
Supported unified formats and equivalent combinations of data and numeric formats
|
|
are defined below:
|
|
|
|
============================== ============================== =============================
|
|
Syntax Equivalent Data Format Equivalent Numeric Format
|
|
============================== ============================== =============================
|
|
BUF_FMT_INVALID BUF_DATA_FORMAT_INVALID BUF_NUM_FORMAT_UNORM
|
|
|
|
BUF_FMT_8_UNORM BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_8_SNORM BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_8_USCALED BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_8_SSCALED BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_8_UINT BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_8_SINT BUF_DATA_FORMAT_8 BUF_NUM_FORMAT_SINT
|
|
|
|
BUF_FMT_16_UNORM BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_16_SNORM BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_16_USCALED BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_16_SSCALED BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_16_UINT BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_16_SINT BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_16_FLOAT BUF_DATA_FORMAT_16 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_8_8_UNORM BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_8_8_SNORM BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_8_8_USCALED BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_8_8_SSCALED BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_8_8_UINT BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_8_8_SINT BUF_DATA_FORMAT_8_8 BUF_NUM_FORMAT_SINT
|
|
|
|
BUF_FMT_32_UINT BUF_DATA_FORMAT_32 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_32_SINT BUF_DATA_FORMAT_32 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_32_FLOAT BUF_DATA_FORMAT_32 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_16_16_UNORM BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_16_16_SNORM BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_16_16_USCALED BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_16_16_SSCALED BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_16_16_UINT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_16_16_SINT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_16_16_FLOAT BUF_DATA_FORMAT_16_16 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_10_11_11_UNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_10_11_11_SNORM BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_10_11_11_USCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_10_11_11_SSCALED BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_10_11_11_UINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_10_11_11_SINT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_10_11_11_FLOAT BUF_DATA_FORMAT_10_11_11 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_11_11_10_UNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_11_11_10_SNORM BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_11_11_10_USCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_11_11_10_SSCALED BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_11_11_10_UINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_11_11_10_SINT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_11_11_10_FLOAT BUF_DATA_FORMAT_11_11_10 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_10_10_10_2_UNORM BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_10_10_10_2_SNORM BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_10_10_10_2_USCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_10_10_10_2_SSCALED BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_10_10_10_2_UINT BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_10_10_10_2_SINT BUF_DATA_FORMAT_10_10_10_2 BUF_NUM_FORMAT_SINT
|
|
|
|
BUF_FMT_2_10_10_10_UNORM BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_2_10_10_10_SNORM BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_2_10_10_10_USCALED BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_2_10_10_10_SSCALED BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_2_10_10_10_UINT BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_2_10_10_10_SINT BUF_DATA_FORMAT_2_10_10_10 BUF_NUM_FORMAT_SINT
|
|
|
|
BUF_FMT_8_8_8_8_UNORM BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_8_8_8_8_SNORM BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_8_8_8_8_USCALED BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_8_8_8_8_SSCALED BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_8_8_8_8_UINT BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_8_8_8_8_SINT BUF_DATA_FORMAT_8_8_8_8 BUF_NUM_FORMAT_SINT
|
|
|
|
BUF_FMT_32_32_UINT BUF_DATA_FORMAT_32_32 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_32_32_SINT BUF_DATA_FORMAT_32_32 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_32_32_FLOAT BUF_DATA_FORMAT_32_32 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_16_16_16_16_UNORM BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_UNORM
|
|
BUF_FMT_16_16_16_16_SNORM BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_SNORM
|
|
BUF_FMT_16_16_16_16_USCALED BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_USCALED
|
|
BUF_FMT_16_16_16_16_SSCALED BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_SSCALED
|
|
BUF_FMT_16_16_16_16_UINT BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_16_16_16_16_SINT BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_16_16_16_16_FLOAT BUF_DATA_FORMAT_16_16_16_16 BUF_NUM_FORMAT_FLOAT
|
|
|
|
BUF_FMT_32_32_32_UINT BUF_DATA_FORMAT_32_32_32 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_32_32_32_SINT BUF_DATA_FORMAT_32_32_32 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_32_32_32_FLOAT BUF_DATA_FORMAT_32_32_32 BUF_NUM_FORMAT_FLOAT
|
|
BUF_FMT_32_32_32_32_UINT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_UINT
|
|
BUF_FMT_32_32_32_32_SINT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_SINT
|
|
BUF_FMT_32_32_32_32_FLOAT BUF_DATA_FORMAT_32_32_32_32 BUF_NUM_FORMAT_FLOAT
|
|
============================== ============================== =============================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
format:0
|
|
format:[BUF_FMT_32_UINT]
|
|
|
|
SMRD/SMEM Modifiers
|
|
-------------------
|
|
|
|
glc
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_glc>`.
|
|
|
|
nv
|
|
~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_nv>`. GFX9 only.
|
|
|
|
dlc
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_dlc>`. GFX10 only.
|
|
|
|
VINTRP Modifiers
|
|
----------------
|
|
|
|
.. _amdgpu_synid_high:
|
|
|
|
high
|
|
~~~~
|
|
|
|
Specifies which half of the LDS word to use. Low half of LDS word is used by default.
|
|
GFX9 and GFX10 only.
|
|
|
|
======================================== ================================
|
|
Syntax Description
|
|
======================================== ================================
|
|
high Use high half of LDS word.
|
|
======================================== ================================
|
|
|
|
DPP8 Modifiers
|
|
--------------
|
|
|
|
GFX10 only.
|
|
|
|
.. _amdgpu_synid_dpp8_sel:
|
|
|
|
dpp8_sel
|
|
~~~~~~~~
|
|
|
|
Selects which lanes to pull data from, within a group of 8 lanes. This is a mandatory modifier.
|
|
There is no default value.
|
|
|
|
GFX10 only.
|
|
|
|
The *dpp8_sel* modifier must specify exactly 8 values.
|
|
First value selects which lane to read from to supply data into lane 0.
|
|
Second value controls lane 1 and so on.
|
|
|
|
Each value may be specified as either
|
|
an :ref:`integer number<amdgpu_synid_integer_number>` or
|
|
an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
|
|
=============================================================== ===========================
|
|
Syntax Description
|
|
=============================================================== ===========================
|
|
dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}] Select lanes to read from.
|
|
=============================================================== ===========================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
dpp8:[7,6,5,4,3,2,1,0]
|
|
dpp8:[0,1,0,1,0,1,0,1]
|
|
|
|
.. _amdgpu_synid_fi8:
|
|
|
|
fi
|
|
~~
|
|
|
|
Controls interaction with inactive lanes for *dpp8* instructions. The default value is zero.
|
|
|
|
Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.
|
|
|
|
GFX10 only.
|
|
|
|
==================================== =====================================================
|
|
Syntax Description
|
|
==================================== =====================================================
|
|
fi:0 Fetch zero when accessing data from inactive lanes.
|
|
fi:1 Fetch pre-exist values from inactive lanes.
|
|
==================================== =====================================================
|
|
|
|
Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
DPP Modifiers
|
|
-------------
|
|
|
|
GFX8, GFX9 and GFX10 only.
|
|
|
|
.. _amdgpu_synid_dpp_ctrl:
|
|
|
|
dpp_ctrl
|
|
~~~~~~~~
|
|
|
|
Specifies how data are shared between threads. This is a mandatory modifier.
|
|
There is no default value.
|
|
|
|
GFX8 and GFX9 only. Use :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` for GFX10.
|
|
|
|
Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
|
|
row_mirror Mirror threads within row.
|
|
row_half_mirror Mirror threads within 1/2 row (8 threads).
|
|
row_bcast:15 Broadcast 15th thread of each row to next row.
|
|
row_bcast:31 Broadcast thread 31 to rows 2 and 3.
|
|
wave_shl:1 Wavefront left shift by 1 thread.
|
|
wave_rol:1 Wavefront left rotate by 1 thread.
|
|
wave_shr:1 Wavefront right shift by 1 thread.
|
|
wave_ror:1 Wavefront right rotate by 1 thread.
|
|
row_shl:{1..15} Row shift left by 1-15 threads.
|
|
row_shr:{1..15} Row shift right by 1-15 threads.
|
|
row_ror:{1..15} Row rotate right by 1-15 threads.
|
|
======================================== ================================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
quad_perm:[0, 1, 2, 3]
|
|
row_shl:3
|
|
|
|
.. _amdgpu_synid_dpp16_ctrl:
|
|
|
|
dpp16_ctrl
|
|
~~~~~~~~~~
|
|
|
|
Specifies how data are shared between threads. This is a mandatory modifier.
|
|
There is no default value.
|
|
|
|
GFX10 only. Use :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` for GFX8 and GFX9.
|
|
|
|
Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
|
|
(There are only two rows in *wave32* mode.)
|
|
|
|
======================================== ====================================================
|
|
Syntax Description
|
|
======================================== ====================================================
|
|
quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
|
|
row_mirror Mirror threads within row.
|
|
row_half_mirror Mirror threads within 1/2 row (8 threads).
|
|
row_share:{0..15} Share the value from the specified lane with other
|
|
lanes in the row.
|
|
row_xmask:{0..15} Fetch from XOR(current lane id, specified lane id).
|
|
row_shl:{1..15} Row shift left by 1-15 threads.
|
|
row_shr:{1..15} Row shift right by 1-15 threads.
|
|
row_ror:{1..15} Row rotate right by 1-15 threads.
|
|
======================================== ====================================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
quad_perm:[0, 1, 2, 3]
|
|
row_shl:3
|
|
|
|
.. _amdgpu_synid_dpp32_ctrl:
|
|
|
|
dpp32_ctrl
|
|
~~~~~~~~~~
|
|
|
|
Specifies how data are shared between threads. This is a mandatory modifier.
|
|
There is no default value.
|
|
|
|
May be used only with GFX90A 32-bit instructions.
|
|
|
|
Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
|
|
|
|
======================================== ==================================================
|
|
Syntax Description
|
|
======================================== ==================================================
|
|
quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
|
|
row_mirror Mirror threads within row.
|
|
row_half_mirror Mirror threads within 1/2 row (8 threads).
|
|
row_bcast:15 Broadcast 15th thread of each row to next row.
|
|
row_bcast:31 Broadcast thread 31 to rows 2 and 3.
|
|
wave_shl:1 Wavefront left shift by 1 thread.
|
|
wave_rol:1 Wavefront left rotate by 1 thread.
|
|
wave_shr:1 Wavefront right shift by 1 thread.
|
|
wave_ror:1 Wavefront right rotate by 1 thread.
|
|
row_shl:{1..15} Row shift left by 1-15 threads.
|
|
row_shr:{1..15} Row shift right by 1-15 threads.
|
|
row_ror:{1..15} Row rotate right by 1-15 threads.
|
|
row_newbcast:{1..15} Broadcast a thread within a row to the whole row.
|
|
======================================== ==================================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
quad_perm:[0, 1, 2, 3]
|
|
row_shl:3
|
|
|
|
|
|
.. _amdgpu_synid_dpp64_ctrl:
|
|
|
|
dpp64_ctrl
|
|
~~~~~~~~~~
|
|
|
|
Specifies how data are shared between threads. This is a mandatory modifier.
|
|
There is no default value.
|
|
|
|
May be used only with GFX90A 64-bit instructions.
|
|
|
|
Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
|
|
|
|
======================================== ==================================================
|
|
Syntax Description
|
|
======================================== ==================================================
|
|
row_newbcast:{1..15} Broadcast a thread within a row to the whole row.
|
|
======================================== ==================================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
row_newbcast:3
|
|
|
|
|
|
.. _amdgpu_synid_row_mask:
|
|
|
|
row_mask
|
|
~~~~~~~~
|
|
|
|
Controls which rows are enabled for data sharing. By default, all rows are enabled.
|
|
|
|
Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
|
|
(There are only two rows in *wave32* mode.)
|
|
|
|
================= ====================================================================
|
|
Syntax Description
|
|
================= ====================================================================
|
|
row_mask:{0..15} Specifies a *row mask* as a positive
|
|
:ref:`integer number <amdgpu_synid_integer_number>`
|
|
or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
|
|
Each of 4 bits in the mask controls one row
|
|
(0 - disabled, 1 - enabled).
|
|
|
|
In *wave32* mode the values should be limited to 0..7.
|
|
================= ====================================================================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
row_mask:0xf
|
|
row_mask:0b1010
|
|
row_mask:x|y
|
|
|
|
.. _amdgpu_synid_bank_mask:
|
|
|
|
bank_mask
|
|
~~~~~~~~~
|
|
|
|
Controls which banks are enabled for data sharing. By default, all banks are enabled.
|
|
|
|
Note: the lanes of a wavefront are organized in four *rows* and four *banks*.
|
|
(There are only two rows in *wave32* mode.)
|
|
|
|
================== ====================================================================
|
|
Syntax Description
|
|
================== ====================================================================
|
|
bank_mask:{0..15} Specifies a *bank mask* as a positive
|
|
:ref:`integer number <amdgpu_synid_integer_number>`
|
|
or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
|
|
Each of 4 bits in the mask controls one bank
|
|
(0 - disabled, 1 - enabled).
|
|
================== ====================================================================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
bank_mask:0x3
|
|
bank_mask:0b0011
|
|
bank_mask:x&y
|
|
|
|
.. _amdgpu_synid_bound_ctrl:
|
|
|
|
bound_ctrl
|
|
~~~~~~~~~~
|
|
|
|
Controls data sharing when accessing an invalid lane. By default, data sharing with
|
|
invalid lanes is disabled.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
bound_ctrl:1 Enables data sharing with invalid lanes.
|
|
|
|
Accessing data from an invalid lane will
|
|
return zero.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_fi16:
|
|
|
|
fi
|
|
~~
|
|
|
|
Controls interaction with *inactive* lanes for *dpp16* instructions. The default value is zero.
|
|
|
|
Note: *inactive* lanes are those whose :ref:`exec<amdgpu_synid_exec>` mask bit is zero.
|
|
|
|
GFX10 only.
|
|
|
|
======================================== ==================================================
|
|
Syntax Description
|
|
======================================== ==================================================
|
|
fi:0 Interaction with inactive lanes is controlled by
|
|
:ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.
|
|
|
|
fi:1 Fetch pre-exist values from inactive lanes.
|
|
======================================== ==================================================
|
|
|
|
Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
SDWA Modifiers
|
|
--------------
|
|
|
|
GFX8, GFX9 and GFX10 only.
|
|
|
|
clamp
|
|
~~~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_clamp>`.
|
|
|
|
omod
|
|
~~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_omod>`.
|
|
|
|
GFX9 and GFX10 only.
|
|
|
|
.. _amdgpu_synid_dst_sel:
|
|
|
|
dst_sel
|
|
~~~~~~~
|
|
|
|
Selects which bits in the destination are affected. By default, all bits are affected.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
dst_sel:DWORD Use bits 31:0.
|
|
dst_sel:BYTE_0 Use bits 7:0.
|
|
dst_sel:BYTE_1 Use bits 15:8.
|
|
dst_sel:BYTE_2 Use bits 23:16.
|
|
dst_sel:BYTE_3 Use bits 31:24.
|
|
dst_sel:WORD_0 Use bits 15:0.
|
|
dst_sel:WORD_1 Use bits 31:16.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_dst_unused:
|
|
|
|
dst_unused
|
|
~~~~~~~~~~
|
|
|
|
Controls what to do with the bits in the destination which are not selected
|
|
by :ref:`dst_sel<amdgpu_synid_dst_sel>`.
|
|
By default, unused bits are preserved.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
dst_unused:UNUSED_PAD Pad with zeros.
|
|
dst_unused:UNUSED_SEXT Sign-extend upper bits, zero lower bits.
|
|
dst_unused:UNUSED_PRESERVE Preserve bits.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_src0_sel:
|
|
|
|
src0_sel
|
|
~~~~~~~~
|
|
|
|
Controls which bits in the src0 are used. By default, all bits are used.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
src0_sel:DWORD Use bits 31:0.
|
|
src0_sel:BYTE_0 Use bits 7:0.
|
|
src0_sel:BYTE_1 Use bits 15:8.
|
|
src0_sel:BYTE_2 Use bits 23:16.
|
|
src0_sel:BYTE_3 Use bits 31:24.
|
|
src0_sel:WORD_0 Use bits 15:0.
|
|
src0_sel:WORD_1 Use bits 31:16.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_src1_sel:
|
|
|
|
src1_sel
|
|
~~~~~~~~
|
|
|
|
Controls which bits in the src1 are used. By default, all bits are used.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
src1_sel:DWORD Use bits 31:0.
|
|
src1_sel:BYTE_0 Use bits 7:0.
|
|
src1_sel:BYTE_1 Use bits 15:8.
|
|
src1_sel:BYTE_2 Use bits 23:16.
|
|
src1_sel:BYTE_3 Use bits 31:24.
|
|
src1_sel:WORD_0 Use bits 15:0.
|
|
src1_sel:WORD_1 Use bits 31:16.
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_sdwa_operand_modifiers:
|
|
|
|
SDWA Operand Modifiers
|
|
----------------------
|
|
|
|
Operand modifiers are not used separately. They are applied to source operands.
|
|
|
|
GFX8, GFX9 and GFX10 only.
|
|
|
|
abs
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_abs>`.
|
|
|
|
neg
|
|
~~~
|
|
|
|
See a description :ref:`here<amdgpu_synid_neg>`.
|
|
|
|
.. _amdgpu_synid_sext:
|
|
|
|
sext
|
|
~~~~
|
|
|
|
Sign-extends value of a (sub-dword) operand to fill all 32 bits.
|
|
Has no effect for 32-bit operands.
|
|
|
|
Valid for integer operands only.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
sext(<operand>) Sign-extend operand value.
|
|
======================================== ================================================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
sext(v4)
|
|
sext(v255)
|
|
|
|
VOP3 Modifiers
|
|
--------------
|
|
|
|
.. _amdgpu_synid_vop3_op_sel:
|
|
|
|
op_sel
|
|
~~~~~~
|
|
|
|
Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
|
|
By default, low bits are used for all operands.
|
|
|
|
The number of values specified with the op_sel modifier must match the number of instruction
|
|
operands (both source and destination). First value controls src0, second value controls src1
|
|
and so on, except that the last value controls destination.
|
|
The value 0 selects the low bits, while 1 selects the high bits.
|
|
|
|
Note: op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
|
|
by op_sel must be 0.
|
|
|
|
GFX9 and GFX10 only.
|
|
|
|
======================================== ============================================================
|
|
Syntax Description
|
|
======================================== ============================================================
|
|
op_sel:[{0..1},{0..1}] Select operand bits for instructions with 1 source operand.
|
|
op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
|
|
op_sel:[{0..1},{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
|
|
======================================== ============================================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
op_sel:[0,0]
|
|
op_sel:[0,1]
|
|
|
|
.. _amdgpu_synid_dpp_op_sel:
|
|
|
|
dpp_op_sel
|
|
~~~~~~~~~~
|
|
|
|
Special version of *op_sel* used for *permlane* opcodes to specify
|
|
dpp-like mode bits - :ref:`fi<amdgpu_synid_fi16>` and
|
|
:ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.
|
|
|
|
GFX10 only.
|
|
|
|
======================================== ============================================================
|
|
Syntax Description
|
|
======================================== ============================================================
|
|
op_sel:[{0..1},{0..1}] First bit specifies :ref:`fi<amdgpu_synid_fi16>`, second
|
|
bit specifies :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`.
|
|
======================================== ============================================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
op_sel:[0,0]
|
|
|
|
.. _amdgpu_synid_clamp:
|
|
|
|
clamp
|
|
~~~~~
|
|
|
|
Clamp meaning depends on instruction.
|
|
|
|
For *v_cmp* instructions, clamp modifier indicates that the compare signals
|
|
if a floating point exception occurs. By default, signaling is disabled.
|
|
Not supported by GFX7.
|
|
|
|
For integer operations, clamp modifier indicates that the result must be clamped
|
|
to the largest and smallest representable value. By default, there is no clamping.
|
|
Integer clamping is not supported by GFX7.
|
|
|
|
For floating point operations, clamp modifier indicates that the result must be clamped
|
|
to the range [0.0, 1.0]. By default, there is no clamping.
|
|
|
|
Note: clamp modifier is applied after :ref:`output modifiers<amdgpu_synid_omod>` (if any).
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
clamp Enables clamping (or signaling).
|
|
======================================== ================================================
|
|
|
|
.. _amdgpu_synid_omod:
|
|
|
|
omod
|
|
~~~~
|
|
|
|
Specifies if an output modifier must be applied to the result.
|
|
By default, no output modifiers are applied.
|
|
|
|
Note: output modifiers are applied before :ref:`clamping<amdgpu_synid_clamp>` (if any).
|
|
|
|
Output modifiers are valid for f32 and f64 floating point results only.
|
|
They must not be used with f16.
|
|
|
|
Note: *v_cvt_f16_f32* is an exception. This instruction produces f16 result
|
|
but accepts output modifiers.
|
|
|
|
======================================== ================================================
|
|
Syntax Description
|
|
======================================== ================================================
|
|
mul:2 Multiply the result by 2.
|
|
mul:4 Multiply the result by 4.
|
|
div:2 Multiply the result by 0.5.
|
|
======================================== ================================================
|
|
|
|
Note: numeric values may be specified as either :ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
mul:2
|
|
mul:x // x must be equal to 2 or 4
|
|
|
|
.. _amdgpu_synid_vop3_operand_modifiers:
|
|
|
|
VOP3 Operand Modifiers
|
|
----------------------
|
|
|
|
Operand modifiers are not used separately. They are applied to source operands.
|
|
|
|
.. _amdgpu_synid_abs:
|
|
|
|
abs
|
|
~~~
|
|
|
|
Computes the absolute value of its operand. Must be applied before :ref:`neg<amdgpu_synid_neg>`
|
|
(if any). Valid for floating point operands only.
|
|
|
|
======================================== ====================================================
|
|
Syntax Description
|
|
======================================== ====================================================
|
|
abs(<operand>) Get the absolute value of a floating-point operand.
|
|
\|<operand>| The same as above (an SP3 syntax).
|
|
======================================== ====================================================
|
|
|
|
Note: avoid using SP3 syntax with operands specified as expressions because the trailing '|'
|
|
may be misinterpreted. Such operands should be enclosed into additional parentheses as shown
|
|
in examples below.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
abs(v36)
|
|
\|v36|
|
|
abs(x|y) // ok
|
|
\|(x|y)| // additional parentheses are required
|
|
|
|
.. _amdgpu_synid_neg:
|
|
|
|
neg
|
|
~~~
|
|
|
|
Computes the negative value of its operand. Must be applied after :ref:`abs<amdgpu_synid_abs>`
|
|
(if any). Valid for floating point operands only.
|
|
|
|
================== ====================================================
|
|
Syntax Description
|
|
================== ====================================================
|
|
neg(<operand>) Get the negative value of a floating-point operand.
|
|
The operand may include an optional
|
|
:ref:`abs<amdgpu_synid_abs>` modifier.
|
|
-<operand> The same as above (an SP3 syntax).
|
|
================== ====================================================
|
|
|
|
Note: SP3 syntax is supported with limitations because of a potential ambiguity.
|
|
Currently it is allowed in the following cases:
|
|
|
|
* Before a register.
|
|
* Before an :ref:`abs<amdgpu_synid_abs>` modifier.
|
|
* Before an SP3 :ref:`abs<amdgpu_synid_abs>` modifier.
|
|
|
|
In all other cases "-" is handled as a part of an expression that follows the sign.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
// Operands with negate modifiers
|
|
neg(v[0])
|
|
neg(1.0)
|
|
neg(abs(v0))
|
|
-v5
|
|
-abs(v5)
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-\|v5|
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// Operands without negate modifiers
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-1
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-x+y
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VOP3P Modifiers
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---------------
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This section describes modifiers of *regular* VOP3P instructions.
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*v_mad_mix\** and *v_fma_mix\**
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instructions use these modifiers :ref:`in a special manner<amdgpu_synid_mad_mix>`.
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GFX9 and GFX10 only.
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.. _amdgpu_synid_op_sel:
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op_sel
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~~~~~~
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Selects the low [15:0] or high [31:16] operand bits as input to the operation
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which results in the lower-half of the destination.
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By default, low bits are used for all operands.
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The number of values specified by the *op_sel* modifier must match the number of source
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operands. First value controls src0, second value controls src1 and so on.
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The value 0 selects the low bits, while 1 selects the high bits.
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================================= =============================================================
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Syntax Description
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================================= =============================================================
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op_sel:[{0..1}] Select operand bits for instructions with 1 source operand.
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op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
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op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
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================================= =============================================================
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Note: numeric values may be specified as either
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:ref:`integer numbers<amdgpu_synid_integer_number>` or
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:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Examples:
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.. parsed-literal::
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op_sel:[0,0]
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op_sel:[0,1,0]
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.. _amdgpu_synid_op_sel_hi:
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op_sel_hi
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~~~~~~~~~
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Selects the low [15:0] or high [31:16] operand bits as input to the operation
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which results in the upper-half of the destination.
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By default, high bits are used for all operands.
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The number of values specified by the *op_sel_hi* modifier must match the number of source
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operands. First value controls src0, second value controls src1 and so on.
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The value 0 selects the low bits, while 1 selects the high bits.
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=================================== =============================================================
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Syntax Description
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=================================== =============================================================
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op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand.
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op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
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op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
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=================================== =============================================================
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Note: numeric values may be specified as either
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:ref:`integer numbers<amdgpu_synid_integer_number>` or
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:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Examples:
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.. parsed-literal::
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op_sel_hi:[0,0]
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op_sel_hi:[0,0,1]
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.. _amdgpu_synid_neg_lo:
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neg_lo
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~~~~~~
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Specifies whether to change sign of operand values selected by
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:ref:`op_sel<amdgpu_synid_op_sel>`. These values are then used
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as input to the operation which results in the upper-half of the destination.
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The number of values specified by this modifier must match the number of source
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operands. First value controls src0, second value controls src1 and so on.
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The value 0 indicates that the corresponding operand value is used unmodified,
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the value 1 indicates that negative value of the operand must be used.
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By default, operand values are used unmodified.
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This modifier is valid for floating point operands only.
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================================ ==================================================================
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Syntax Description
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================================ ==================================================================
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neg_lo:[{0..1}] Select affected operands for instructions with 1 source operand.
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neg_lo:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
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neg_lo:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
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================================ ==================================================================
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Note: numeric values may be specified as either
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:ref:`integer numbers<amdgpu_synid_integer_number>` or
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:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Examples:
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.. parsed-literal::
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neg_lo:[0]
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neg_lo:[0,1]
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.. _amdgpu_synid_neg_hi:
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neg_hi
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~~~~~~
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Specifies whether to change sign of operand values selected by
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:ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`. These values are then used
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as input to the operation which results in the upper-half of the destination.
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The number of values specified by this modifier must match the number of source
|
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operands. First value controls src0, second value controls src1 and so on.
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The value 0 indicates that the corresponding operand value is used unmodified,
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the value 1 indicates that negative value of the operand must be used.
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By default, operand values are used unmodified.
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This modifier is valid for floating point operands only.
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=============================== ==================================================================
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Syntax Description
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=============================== ==================================================================
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neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.
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neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
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neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
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=============================== ==================================================================
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Note: numeric values may be specified as either
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:ref:`integer numbers<amdgpu_synid_integer_number>` or
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:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Examples:
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.. parsed-literal::
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neg_hi:[1,0]
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neg_hi:[0,1,1]
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clamp
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~~~~~
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See a description :ref:`here<amdgpu_synid_clamp>`.
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.. _amdgpu_synid_mad_mix:
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VOP3P MAD_MIX/FMA_MIX Modifiers
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-------------------------------
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*v_mad_mix\** and *v_fma_mix\**
|
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instructions use *op_sel* and *op_sel_hi* modifiers
|
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in a manner different from *regular* VOP3P instructions.
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See a description below.
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GFX9 and GFX10 only.
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.. _amdgpu_synid_mad_mix_op_sel:
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m_op_sel
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~~~~~~~~
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This operand has meaning only for 16-bit source operands as indicated by
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:ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
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It specifies to select either the low [15:0] or high [31:16] operand bits
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as input to the operation.
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The number of values specified by the *op_sel* modifier must match the number of source
|
|
operands. First value controls src0, second value controls src1 and so on.
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The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
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By default, low bits are used for all operands.
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=============================== ================================================
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Syntax Description
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=============================== ================================================
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op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
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=============================== ================================================
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Note: numeric values may be specified as either
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:ref:`integer numbers<amdgpu_synid_integer_number>` or
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:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Examples:
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.. parsed-literal::
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op_sel:[0,1]
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.. _amdgpu_synid_mad_mix_op_sel_hi:
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m_op_sel_hi
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~~~~~~~~~~~
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Selects the size of source operands: either 32 bits or 16 bits.
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By default, 32 bits are used for all source operands.
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The number of values specified by the *op_sel_hi* modifier must match the number of source
|
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operands. First value controls src0, second value controls src1 and so on.
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The value 0 indicates 32 bits, the value 1 indicates 16 bits.
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The location of 16 bits in the operand may be specified by
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:ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
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======================================== ====================================
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|
Syntax Description
|
|
======================================== ====================================
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op_sel_hi:[{0..1},{0..1},{0..1}] Select size of each source operand.
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|
======================================== ====================================
|
|
|
|
Note: numeric values may be specified as either
|
|
:ref:`integer numbers<amdgpu_synid_integer_number>` or
|
|
:ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
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op_sel_hi:[1,1,1]
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abs
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~~~
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See a description :ref:`here<amdgpu_synid_abs>`.
|
|
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neg
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~~~
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See a description :ref:`here<amdgpu_synid_neg>`.
|
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clamp
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~~~~~
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See a description :ref:`here<amdgpu_synid_clamp>`.
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VOP3P MFMA Modifiers
|
|
--------------------
|
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These modifiers may only be used with GFX908 and GFX90A.
|
|
|
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.. _amdgpu_synid_cbsz:
|
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cbsz
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~~~~
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Specifies a broadcast mode.
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=============================== ==================================================================
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Syntax Description
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|
=============================== ==================================================================
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cbsz:[{0..7}] A broadcast mode.
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=============================== ==================================================================
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|
|
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Note: numeric value may be specified as either
|
|
an :ref:`integer number<amdgpu_synid_integer_number>` or
|
|
an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
|
|
.. _amdgpu_synid_abid:
|
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|
|
abid
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|
~~~~
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Specifies matrix A group select.
|
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=============================== ==================================================================
|
|
Syntax Description
|
|
=============================== ==================================================================
|
|
abid:[{0..15}] Matrix A group select id.
|
|
=============================== ==================================================================
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|
|
|
Note: numeric value may be specified as either
|
|
an :ref:`integer number<amdgpu_synid_integer_number>` or
|
|
an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
|
|
.. _amdgpu_synid_blgp:
|
|
|
|
blgp
|
|
~~~~
|
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|
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Specifies matrix B lane group pattern.
|
|
|
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=============================== ==================================================================
|
|
Syntax Description
|
|
=============================== ==================================================================
|
|
blgp:[{0..7}] Matrix B lane group pattern.
|
|
=============================== ==================================================================
|
|
|
|
Note: numeric value may be specified as either
|
|
an :ref:`integer number<amdgpu_synid_integer_number>` or
|
|
an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
|
|
|