565 lines
16 KiB
C++
565 lines
16 KiB
C++
//===-------------- BPFMIPeephole.cpp - MI Peephole Cleanups -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs peephole optimizations to cleanup ugly code sequences at
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// MachineInstruction layer.
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//
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// Currently, there are two optimizations implemented:
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// - One pre-RA MachineSSA pass to eliminate type promotion sequences, those
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// zero extend 32-bit subregisters to 64-bit registers, if the compiler
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// could prove the subregisters is defined by 32-bit operations in which
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// case the upper half of the underlying 64-bit registers were zeroed
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// implicitly.
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//
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// - One post-RA PreEmit pass to do final cleanup on some redundant
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// instructions generated due to bad RA on subregister.
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "BPFInstrInfo.h"
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#include "BPFTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include <set>
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using namespace llvm;
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#define DEBUG_TYPE "bpf-mi-zext-elim"
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STATISTIC(ZExtElemNum, "Number of zero extension shifts eliminated");
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namespace {
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struct BPFMIPeephole : public MachineFunctionPass {
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static char ID;
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const BPFInstrInfo *TII;
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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BPFMIPeephole() : MachineFunctionPass(ID) {
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initializeBPFMIPeepholePass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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bool isCopyFrom32Def(MachineInstr *CopyMI);
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bool isInsnFrom32Def(MachineInstr *DefInsn);
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bool isPhiFrom32Def(MachineInstr *MovMI);
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bool isMovFrom32Def(MachineInstr *MovMI);
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bool eliminateZExtSeq();
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bool eliminateZExt();
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std::set<MachineInstr *> PhiInsns;
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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initialize(MF);
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// First try to eliminate (zext, lshift, rshift) and then
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// try to eliminate zext.
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bool ZExtSeqExist, ZExtExist;
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ZExtSeqExist = eliminateZExtSeq();
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ZExtExist = eliminateZExt();
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return ZExtSeqExist || ZExtExist;
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}
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};
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// Initialize class variables.
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void BPFMIPeephole::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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MRI = &MF->getRegInfo();
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TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
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LLVM_DEBUG(dbgs() << "*** BPF MachineSSA ZEXT Elim peephole pass ***\n\n");
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}
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bool BPFMIPeephole::isCopyFrom32Def(MachineInstr *CopyMI)
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{
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MachineOperand &opnd = CopyMI->getOperand(1);
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if (!opnd.isReg())
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return false;
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// Return false if getting value from a 32bit physical register.
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// Most likely, this physical register is aliased to
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// function call return value or current function parameters.
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Register Reg = opnd.getReg();
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if (!Register::isVirtualRegister(Reg))
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return false;
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if (MRI->getRegClass(Reg) == &BPF::GPRRegClass)
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return false;
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MachineInstr *DefInsn = MRI->getVRegDef(Reg);
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if (!isInsnFrom32Def(DefInsn))
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return false;
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return true;
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}
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bool BPFMIPeephole::isPhiFrom32Def(MachineInstr *PhiMI)
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{
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for (unsigned i = 1, e = PhiMI->getNumOperands(); i < e; i += 2) {
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MachineOperand &opnd = PhiMI->getOperand(i);
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if (!opnd.isReg())
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return false;
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MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
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if (!PhiDef)
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return false;
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if (PhiDef->isPHI()) {
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if (PhiInsns.find(PhiDef) != PhiInsns.end())
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return false;
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PhiInsns.insert(PhiDef);
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if (!isPhiFrom32Def(PhiDef))
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return false;
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}
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if (PhiDef->getOpcode() == BPF::COPY && !isCopyFrom32Def(PhiDef))
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return false;
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}
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return true;
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}
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// The \p DefInsn instruction defines a virtual register.
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bool BPFMIPeephole::isInsnFrom32Def(MachineInstr *DefInsn)
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{
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if (!DefInsn)
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return false;
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if (DefInsn->isPHI()) {
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if (PhiInsns.find(DefInsn) != PhiInsns.end())
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return false;
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PhiInsns.insert(DefInsn);
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if (!isPhiFrom32Def(DefInsn))
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return false;
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} else if (DefInsn->getOpcode() == BPF::COPY) {
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if (!isCopyFrom32Def(DefInsn))
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return false;
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}
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return true;
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}
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bool BPFMIPeephole::isMovFrom32Def(MachineInstr *MovMI)
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{
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MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
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LLVM_DEBUG(dbgs() << " Def of Mov Src:");
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LLVM_DEBUG(DefInsn->dump());
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PhiInsns.clear();
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if (!isInsnFrom32Def(DefInsn))
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return false;
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LLVM_DEBUG(dbgs() << " One ZExt elim sequence identified.\n");
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return true;
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}
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bool BPFMIPeephole::eliminateZExtSeq() {
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MachineInstr* ToErase = nullptr;
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bool Eliminated = false;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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// If the previous instruction was marked for elimination, remove it now.
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// Eliminate the 32-bit to 64-bit zero extension sequence when possible.
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//
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// MOV_32_64 rB, wA
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// SLL_ri rB, rB, 32
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// SRL_ri rB, rB, 32
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if (MI.getOpcode() == BPF::SRL_ri &&
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MI.getOperand(2).getImm() == 32) {
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Register DstReg = MI.getOperand(0).getReg();
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Register ShfReg = MI.getOperand(1).getReg();
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MachineInstr *SllMI = MRI->getVRegDef(ShfReg);
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LLVM_DEBUG(dbgs() << "Starting SRL found:");
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LLVM_DEBUG(MI.dump());
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if (!SllMI ||
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SllMI->isPHI() ||
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SllMI->getOpcode() != BPF::SLL_ri ||
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SllMI->getOperand(2).getImm() != 32)
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continue;
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LLVM_DEBUG(dbgs() << " SLL found:");
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LLVM_DEBUG(SllMI->dump());
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MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
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if (!MovMI ||
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MovMI->isPHI() ||
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MovMI->getOpcode() != BPF::MOV_32_64)
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continue;
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LLVM_DEBUG(dbgs() << " Type cast Mov found:");
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LLVM_DEBUG(MovMI->dump());
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Register SubReg = MovMI->getOperand(1).getReg();
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if (!isMovFrom32Def(MovMI)) {
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LLVM_DEBUG(dbgs()
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<< " One ZExt elim sequence failed qualifying elim.\n");
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continue;
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}
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
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.addImm(0).addReg(SubReg).addImm(BPF::sub_32);
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SllMI->eraseFromParent();
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MovMI->eraseFromParent();
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// MI is the right shift, we can't erase it in it's own iteration.
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// Mark it to ToErase, and erase in the next iteration.
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ToErase = &MI;
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ZExtElemNum++;
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Eliminated = true;
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}
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}
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}
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return Eliminated;
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}
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bool BPFMIPeephole::eliminateZExt() {
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MachineInstr* ToErase = nullptr;
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bool Eliminated = false;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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// If the previous instruction was marked for elimination, remove it now.
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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if (MI.getOpcode() != BPF::MOV_32_64)
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continue;
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// Eliminate MOV_32_64 if possible.
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// MOV_32_64 rA, wB
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//
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// If wB has been zero extended, replace it with a SUBREG_TO_REG.
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// This is to workaround BPF programs where pkt->{data, data_end}
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// is encoded as u32, but actually the verifier populates them
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// as 64bit pointer. The MOV_32_64 will zero out the top 32 bits.
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LLVM_DEBUG(dbgs() << "Candidate MOV_32_64 instruction:");
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LLVM_DEBUG(MI.dump());
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if (!isMovFrom32Def(&MI))
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continue;
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LLVM_DEBUG(dbgs() << "Removing the MOV_32_64 instruction\n");
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Register dst = MI.getOperand(0).getReg();
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Register src = MI.getOperand(1).getReg();
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// Build a SUBREG_TO_REG instruction.
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), dst)
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.addImm(0).addReg(src).addImm(BPF::sub_32);
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ToErase = &MI;
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Eliminated = true;
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}
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}
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return Eliminated;
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}
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} // end default namespace
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INITIALIZE_PASS(BPFMIPeephole, DEBUG_TYPE,
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"BPF MachineSSA Peephole Optimization For ZEXT Eliminate",
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false, false)
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char BPFMIPeephole::ID = 0;
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FunctionPass* llvm::createBPFMIPeepholePass() { return new BPFMIPeephole(); }
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STATISTIC(RedundantMovElemNum, "Number of redundant moves eliminated");
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namespace {
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struct BPFMIPreEmitPeephole : public MachineFunctionPass {
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static char ID;
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MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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BPFMIPreEmitPeephole() : MachineFunctionPass(ID) {
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initializeBPFMIPreEmitPeepholePass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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bool eliminateRedundantMov();
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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initialize(MF);
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return eliminateRedundantMov();
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}
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};
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// Initialize class variables.
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void BPFMIPreEmitPeephole::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo();
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LLVM_DEBUG(dbgs() << "*** BPF PreEmit peephole pass ***\n\n");
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}
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bool BPFMIPreEmitPeephole::eliminateRedundantMov() {
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MachineInstr* ToErase = nullptr;
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bool Eliminated = false;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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// If the previous instruction was marked for elimination, remove it now.
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if (ToErase) {
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LLVM_DEBUG(dbgs() << " Redundant Mov Eliminated:");
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LLVM_DEBUG(ToErase->dump());
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// Eliminate identical move:
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//
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// MOV rA, rA
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//
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// Note that we cannot remove
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// MOV_32_64 rA, wA
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// MOV_rr_32 wA, wA
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// as these two instructions having side effects, zeroing out
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// top 32 bits of rA.
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unsigned Opcode = MI.getOpcode();
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if (Opcode == BPF::MOV_rr) {
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Register dst = MI.getOperand(0).getReg();
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Register src = MI.getOperand(1).getReg();
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if (dst != src)
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continue;
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ToErase = &MI;
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RedundantMovElemNum++;
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Eliminated = true;
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}
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}
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}
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return Eliminated;
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}
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} // end default namespace
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INITIALIZE_PASS(BPFMIPreEmitPeephole, "bpf-mi-pemit-peephole",
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"BPF PreEmit Peephole Optimization", false, false)
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char BPFMIPreEmitPeephole::ID = 0;
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FunctionPass* llvm::createBPFMIPreEmitPeepholePass()
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{
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return new BPFMIPreEmitPeephole();
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}
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STATISTIC(TruncElemNum, "Number of truncation eliminated");
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namespace {
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struct BPFMIPeepholeTruncElim : public MachineFunctionPass {
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static char ID;
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const BPFInstrInfo *TII;
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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BPFMIPeepholeTruncElim() : MachineFunctionPass(ID) {
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initializeBPFMIPeepholeTruncElimPass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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bool eliminateTruncSeq();
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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initialize(MF);
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return eliminateTruncSeq();
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}
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};
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static bool TruncSizeCompatible(int TruncSize, unsigned opcode)
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{
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if (TruncSize == 1)
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return opcode == BPF::LDB || opcode == BPF::LDB32;
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if (TruncSize == 2)
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return opcode == BPF::LDH || opcode == BPF::LDH32;
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if (TruncSize == 4)
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return opcode == BPF::LDW || opcode == BPF::LDW32;
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return false;
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}
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// Initialize class variables.
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void BPFMIPeepholeTruncElim::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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MRI = &MF->getRegInfo();
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TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
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LLVM_DEBUG(dbgs() << "*** BPF MachineSSA TRUNC Elim peephole pass ***\n\n");
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}
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// Reg truncating is often the result of 8/16/32bit->64bit or
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// 8/16bit->32bit conversion. If the reg value is loaded with
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// masked byte width, the AND operation can be removed since
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// BPF LOAD already has zero extension.
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//
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// This also solved a correctness issue.
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// In BPF socket-related program, e.g., __sk_buff->{data, data_end}
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// are 32-bit registers, but later on, kernel verifier will rewrite
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// it with 64-bit value. Therefore, truncating the value after the
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// load will result in incorrect code.
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bool BPFMIPeepholeTruncElim::eliminateTruncSeq() {
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MachineInstr* ToErase = nullptr;
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bool Eliminated = false;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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// The second insn to remove if the eliminate candidate is a pair.
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MachineInstr *MI2 = nullptr;
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Register DstReg, SrcReg;
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MachineInstr *DefMI;
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int TruncSize = -1;
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// If the previous instruction was marked for elimination, remove it now.
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// AND A, 0xFFFFFFFF will be turned into SLL/SRL pair due to immediate
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// for BPF ANDI is i32, and this case only happens on ALU64.
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if (MI.getOpcode() == BPF::SRL_ri &&
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MI.getOperand(2).getImm() == 32) {
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SrcReg = MI.getOperand(1).getReg();
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if (!MRI->hasOneNonDBGUse(SrcReg))
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continue;
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MI2 = MRI->getVRegDef(SrcReg);
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DstReg = MI.getOperand(0).getReg();
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if (!MI2 ||
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MI2->getOpcode() != BPF::SLL_ri ||
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MI2->getOperand(2).getImm() != 32)
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continue;
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// Update SrcReg.
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SrcReg = MI2->getOperand(1).getReg();
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DefMI = MRI->getVRegDef(SrcReg);
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if (DefMI)
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TruncSize = 4;
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} else if (MI.getOpcode() == BPF::AND_ri ||
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MI.getOpcode() == BPF::AND_ri_32) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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DefMI = MRI->getVRegDef(SrcReg);
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if (!DefMI)
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continue;
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int64_t imm = MI.getOperand(2).getImm();
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if (imm == 0xff)
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TruncSize = 1;
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else if (imm == 0xffff)
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TruncSize = 2;
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}
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if (TruncSize == -1)
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continue;
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// The definition is PHI node, check all inputs.
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if (DefMI->isPHI()) {
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bool CheckFail = false;
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for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) {
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MachineOperand &opnd = DefMI->getOperand(i);
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if (!opnd.isReg()) {
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CheckFail = true;
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break;
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}
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MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
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if (!PhiDef || PhiDef->isPHI() ||
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!TruncSizeCompatible(TruncSize, PhiDef->getOpcode())) {
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|
CheckFail = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (CheckFail)
|
|
continue;
|
|
} else if (!TruncSizeCompatible(TruncSize, DefMI->getOpcode())) {
|
|
continue;
|
|
}
|
|
|
|
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::MOV_rr), DstReg)
|
|
.addReg(SrcReg);
|
|
|
|
if (MI2)
|
|
MI2->eraseFromParent();
|
|
|
|
// Mark it to ToErase, and erase in the next iteration.
|
|
ToErase = &MI;
|
|
TruncElemNum++;
|
|
Eliminated = true;
|
|
}
|
|
}
|
|
|
|
return Eliminated;
|
|
}
|
|
|
|
} // end default namespace
|
|
|
|
INITIALIZE_PASS(BPFMIPeepholeTruncElim, "bpf-mi-trunc-elim",
|
|
"BPF MachineSSA Peephole Optimization For TRUNC Eliminate",
|
|
false, false)
|
|
|
|
char BPFMIPeepholeTruncElim::ID = 0;
|
|
FunctionPass* llvm::createBPFMIPeepholeTruncElimPass()
|
|
{
|
|
return new BPFMIPeepholeTruncElim();
|
|
}
|