366 lines
16 KiB
TableGen
366 lines
16 KiB
TableGen
//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the PowerPC 32- and 64-bit
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// architectures.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("static_cast<const PPCSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).",
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F),
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A>;
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class CCIfNotSubtarget<string F, CCAction A>
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: CCIf<!strconcat("!static_cast<const PPCSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).",
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F),
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A>;
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class CCIfOrigArgWasNotPPCF128<CCAction A>
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: CCIf<"!static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)",
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A>;
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class CCIfOrigArgWasPPCF128<CCAction A>
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: CCIf<"static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)",
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A>;
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//===----------------------------------------------------------------------===//
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// Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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// PPC64 AnyReg return-value convention. No explicit register is specified for
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// the return-value. The register allocator is allowed and expected to choose
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// any free register.
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//
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// This calling convention is currently only supported by the stackmap and
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// patchpoint intrinsics. All other uses will result in an assert on Debug
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// builds. On Release builds we fallback to the PPC C calling convention.
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def RetCC_PPC64_AnyReg : CallingConv<[
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CCCustom<"CC_PPC_AnyReg_Error">
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]>;
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// Return-value convention for PowerPC coldcc.
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let Entry = 1 in
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def RetCC_PPC_Cold : CallingConv<[
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// Use the same return registers as RetCC_PPC, but limited to only
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// one return value. The remaining return values will be saved to
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// the stack.
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CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
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CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
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CCIfType<[i32], CCAssignToReg<[R3]>>,
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CCIfType<[i64], CCAssignToReg<[X3]>>,
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CCIfType<[i128], CCAssignToReg<[X3]>>,
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CCIfType<[f32], CCAssignToReg<[F1]>>,
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CCIfType<[f64], CCAssignToReg<[F1]>>,
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CCIfType<[f128], CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2]>>>,
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
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CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2]>>>
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]>;
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// Return-value convention for PowerPC
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let Entry = 1 in
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def RetCC_PPC : CallingConv<[
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
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// On PPC64, integer return values are always promoted to i64
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CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
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CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
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// Floating point types returned as "direct" go into F1 .. F8; note that
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// only the ELFv2 ABI fully utilizes all these registers.
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CCIfNotSubtarget<"hasSPE()",
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CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
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CCIfNotSubtarget<"hasSPE()",
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CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
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CCIfSubtarget<"hasSPE()",
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CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
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CCIfSubtarget<"hasSPE()",
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CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>,
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// For P9, f128 are passed in vector registers.
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CCIfType<[f128],
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CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
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// Vector types returned as "direct" go into V2 .. V9; note that only the
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// ELFv2 ABI fully utilizes all these registers.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
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CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
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]>;
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// No explicit register is specified for the AnyReg calling convention. The
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// register allocator may assign the arguments to any free register.
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//
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// This calling convention is currently only supported by the stackmap and
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// patchpoint intrinsics. All other uses will result in an assert on Debug
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// builds. On Release builds we fallback to the PPC C calling convention.
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def CC_PPC64_AnyReg : CallingConv<[
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CCCustom<"CC_PPC_AnyReg_Error">
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]>;
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// Note that we don't currently have calling conventions for 64-bit
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// PowerPC, but handle all the complexities of the ABI in the lowering
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// logic. FIXME: See if the logic can be simplified with use of CCs.
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// This may require some extensions to current table generation.
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// Simple calling convention for 64-bit ELF PowerPC fast isel.
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// Only handle ints and floats. All ints are promoted to i64.
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// Vector types and quadword ints are not handled.
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let Entry = 1 in
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def CC_PPC64_ELF_FIS : CallingConv<[
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
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CCIfType<[i1], CCPromoteToType<i64>>,
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
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]>;
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// Simple return-value convention for 64-bit ELF PowerPC fast isel.
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// All small ints are promoted to i64. Vector types, quadword ints,
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// and multiple register returns are "supported" to avoid compile
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// errors, but none are handled by the fast selector.
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let Entry = 1 in
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def RetCC_PPC64_ELF_FIS : CallingConv<[
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
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CCIfType<[i1], CCPromoteToType<i64>>,
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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CCIfType<[f128],
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CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
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CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// PowerPC System V Release 4 32-bit ABI
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//===----------------------------------------------------------------------===//
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def CC_PPC32_SVR4_Common : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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// The ABI requires i64 to be passed in two adjacent registers with the first
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// register having an odd register number.
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CCIfType<[i32],
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CCIfSplit<CCIfSubtarget<"useSoftFloat()",
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CCIfOrigArgWasNotPPCF128<
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CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>>,
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CCIfType<[i32],
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CCIfSplit<CCIfNotSubtarget<"useSoftFloat()",
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CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>,
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CCIfType<[f64],
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CCIfSubtarget<"hasSPE()",
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CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
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CCIfSplit<CCIfSubtarget<"useSoftFloat()",
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CCIfOrigArgWasPPCF128<CCCustom<
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"CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>,
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// The 'nest' parameter, if any, is passed in R11.
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CCIfNest<CCAssignToReg<[R11]>>,
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// The first 8 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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// Make sure the i64 words from a long double are either both passed in
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// registers or both passed on the stack.
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CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
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// FP values are passed in F1 - F8.
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CCIfType<[f32, f64],
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CCIfNotSubtarget<"hasSPE()",
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CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
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CCIfType<[f64],
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CCIfSubtarget<"hasSPE()",
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CCCustom<"CC_PPC32_SPE_CustomSplitFP64">>>,
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CCIfType<[f32],
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CCIfSubtarget<"hasSPE()",
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
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// Split arguments have an alignment of 8 bytes on the stack.
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CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
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CCIfType<[i32], CCAssignToStack<4, 4>>,
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// Floats are stored in double precision format, thus they have the same
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// alignment and size as doubles.
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// With SPE floats are stored as single precision, so have alignment and
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// size of int.
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CCIfType<[f32,f64], CCIfNotSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>,
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CCIfType<[f32], CCIfSubtarget<"hasSPE()", CCAssignToStack<4, 4>>>,
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CCIfType<[f64], CCIfSubtarget<"hasSPE()", CCAssignToStack<8, 8>>>,
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// Vectors and float128 get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,
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CCIfType<[f128], CCIfSubtarget<"hasAltivec()", CCAssignToStack<16, 16>>>
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]>;
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// This calling convention puts vector arguments always on the stack. It is used
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// to assign vector arguments which belong to the variable portion of the
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// parameter list of a variable argument function.
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let Entry = 1 in
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def CC_PPC32_SVR4_VarArg : CallingConv<[
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CCDelegateTo<CC_PPC32_SVR4_Common>
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]>;
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// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
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// put vector arguments in vector registers before putting them on the stack.
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let Entry = 1 in
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def CC_PPC32_SVR4 : CallingConv<[
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// The first 12 Vector arguments are passed in AltiVec registers.
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
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CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,
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V8, V9, V10, V11, V12, V13]>>>,
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// Float128 types treated as vector arguments.
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CCIfType<[f128],
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CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,
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V8, V9, V10, V11, V12, V13]>>>,
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CCDelegateTo<CC_PPC32_SVR4_Common>
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]>;
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// Helper "calling convention" to handle aggregate by value arguments.
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// Aggregate by value arguments are always placed in the local variable space
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// of the caller. This calling convention is only used to assign those stack
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// offsets in the callers stack frame.
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//
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// Still, the address of the aggregate copy in the callers stack frame is passed
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// in a GPR (or in the parameter list area if all GPRs are allocated) from the
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// caller to the callee. The location for the address argument is assigned by
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// the CC_PPC32_SVR4 calling convention.
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//
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// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
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// not passed by value.
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let Entry = 1 in
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def CC_PPC32_SVR4_ByVal : CallingConv<[
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CCIfByVal<CCPassByVal<4, 4>>,
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CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
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]>;
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def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
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V28, V29, V30, V31)>;
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// SPE does not use FPRs, so break out the common register set as base.
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def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27,
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R28, R29, R30, R31, CR2, CR3, CR4
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)>;
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def CSR_SVR432 : CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31
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)>;
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def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
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S23, S24, S25, S26, S27, S28, S29, S30, S31
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)>;
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def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
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def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
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def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28,
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R29, R30, R31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_AIX32_Altivec : CalleeSavedRegs<(add CSR_AIX32, CSR_Altivec)>;
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// Common CalleeSavedRegs for SVR4 and AIX.
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def CSR_PPC64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
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X21, X22, X23, X24, X25, X26, X27, X28,
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X29, X30, X31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_PPC64_Altivec : CalleeSavedRegs<(add CSR_PPC64, CSR_Altivec)>;
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def CSR_PPC64_R2 : CalleeSavedRegs<(add CSR_PPC64, X2)>;
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def CSR_PPC64_R2_Altivec : CalleeSavedRegs<(add CSR_PPC64_Altivec, X2)>;
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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// coldcc calling convection marks most registers as non-volatile.
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// Do not include r1 since the stack pointer is never considered a CSR.
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// Do not include r2, since it is the TOC register and is added depending
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// on whether or not the function uses the TOC and is a non-leaf.
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// Do not include r0,r11,r13 as they are optional in functional linkage
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// and value may be altered by inter-library calls.
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// Do not include r12 as it is used as a scratch register.
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// Do not include return registers r3, f1, v2.
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def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
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(sequence "R%u", 14, 31),
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(sequence "CR%u", 0, 7))>;
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def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
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F0, (sequence "F%u", 2, 31))>;
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def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC,
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(sequence "V%u", 0, 1),
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(sequence "V%u", 3, 31))>;
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def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
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(sequence "S%u", 4, 10),
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(sequence "S%u", 14, 31))>;
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def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10),
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(sequence "X%u", 14, 31),
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F0, (sequence "F%u", 2, 31),
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(sequence "CR%u", 0, 7))>;
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def CSR_SVR64_ColdCC_R2: CalleeSavedRegs<(add CSR_SVR64_ColdCC, X2)>;
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def CSR_SVR64_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC,
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(sequence "V%u", 0, 1),
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(sequence "V%u", 3, 31))>;
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def CSR_SVR64_ColdCC_R2_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC_Altivec, X2)>;
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def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),
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(sequence "X%u", 14, 31),
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(sequence "F%u", 0, 31),
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(sequence "CR%u", 0, 7))>;
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def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
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(sequence "V%u", 0, 31))>;
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def CSR_64_AllRegs_AIX_Dflt_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
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(sequence "V%u", 0, 19))>;
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def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
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(sequence "VSL%u", 0, 31))>;
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def CSR_64_AllRegs_AIX_Dflt_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
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(sequence "VSL%u", 0, 19))>;
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