llvm-project/llvm/lib/Target/RISCV
Zakk Chen 093ecccdab [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics.
The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D119686
2022-02-17 02:21:39 -08:00
..
AsmParser Cleanup MCParser headers 2022-02-11 10:39:29 +01:00
Disassembler Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
MCTargetDesc [NFC][MC] remove unused argument `MCRegisterInfo` in `MCCodeEmitter` 2022-02-16 13:10:09 +08:00
TargetInfo Fix shlib builds for all lib/Target/*/TargetInfo libs 2021-10-08 15:21:13 -07:00
CMakeLists.txt [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.h [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.td [RISCV] Recover the implication between Zve* extensions and the V extension. 2022-02-14 15:52:07 +08:00
RISCVAsmPrinter.cpp Move TargetRegistry.(h|cpp) from Support to MC 2021-10-08 14:51:48 -07:00
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVCallingConv.td
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVFrameLowering.h Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp [RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values. 2022-01-04 10:13:34 -08:00
RISCVISelDAGToDAG.cpp [RISCV] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds 2022-02-10 20:10:12 -08:00
RISCVISelDAGToDAG.h [RISCV] Select unmasked RVV pseudos in a DAG post-process 2022-02-09 07:50:15 +00:00
RISCVISelLowering.cpp [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
RISCVISelLowering.h [RISCV] Add the passthru operand for RVV nomask binary intrinsics. 2022-02-15 18:36:18 -08:00
RISCVInsertVSETVLI.cpp [RISCV] Insert VSETVLI at the end of a basic block if we didn't produce BlockInfo.Exit. 2022-02-11 09:34:16 -08:00
RISCVInstrFormats.td [RISCV] Add strictfp support for compares. 2022-01-11 20:01:41 -08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td [RISCV] Remove Zvamo Extention 2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
RISCVInstrInfo.h [MachineOutliner] NFC: Hide LRU-related stuff behind helper functions 2022-02-16 11:39:07 -08:00
RISCVInstrInfo.td [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
RISCVInstrInfoA.td [RISCV] Use tablegen size for getInstSizeInBytes. 2022-01-28 09:21:28 -08:00
RISCVInstrInfoC.td [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets 2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
RISCVInstrInfoF.td [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
RISCVInstrInfoM.td [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td [RISCV] Remove Zvlsseg extension. 2022-01-20 12:40:07 -08:00
RISCVInstrInfoVPseudos.td [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics. 2022-02-17 02:21:39 -08:00
RISCVInstrInfoVSDPatterns.td [RISCV] Pre-process FP SPLAT_VECTOR to RISCVISD::VFMV_V_F_VL 2022-02-10 09:56:00 +00:00
RISCVInstrInfoVVLPatterns.td [RISCV] Add the passthru operand for RVV nomask binary intrinsics. 2022-02-15 18:36:18 -08:00
RISCVInstrInfoZb.td [RISCV][NFC] Move some combine patterns to DAG combine. 2022-02-12 02:52:21 +00:00
RISCVInstrInfoZfh.td Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)." 2022-02-05 12:51:01 -08:00
RISCVInstrInfoZk.td [RISCV] Adjust some comments. 2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp [Target] Remove redundant member initialization (NFC) 2022-01-06 22:01:44 -08:00
RISCVLegalizerInfo.cpp [globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one 2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
RISCVMCInstLower.cpp [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
RISCVMachineFunctionInfo.h
RISCVMergeBaseOffset.cpp [RISCV] Remove unused member variable. NFC 2021-10-14 12:56:47 -07:00
RISCVRedundantCopyElimination.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp Revert "[llvm] Remove redundant member initialization (NFC)" 2022-01-03 11:28:47 -08:00
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp Reduce dependencies on llvm/BinaryFormat/Dwarf.h 2022-02-04 11:44:03 +01:00
RISCVRegisterInfo.h [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVSExtWRemoval.cpp [RISCV] Add FMV_X_W and FMV_X_H to RISCVSExtWRemoval. 2022-02-03 09:40:47 -08:00
RISCVSchedRocket.td [RISCV] add support for zbkx subextension in MC layer. 2022-01-24 20:38:46 +08:00
RISCVSchedSiFive7.td [RISCV] add support for zbkx subextension in MC layer. 2022-01-24 20:38:46 +08:00
RISCVSchedule.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVScheduleB.td [RISCV] Add instruction schedule for Zbc extension and Zbs extension 2022-01-18 07:31:50 +00:00
RISCVScheduleV.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp [RISCV] Fix support of vlen = 64. 2022-01-26 16:31:21 +08:00
RISCVSubtarget.h [RISCV] Recover the implication between Zve* extensions and the V extension. 2022-02-14 15:52:07 +08:00
RISCVSystemOperands.td [RISCV] Initially support the K-extension instructions on the LLVM MC layer 2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp [RISCV] Add a really basic cost model for SK_Splice. 2022-02-09 11:43:31 -08:00
RISCVTargetTransformInfo.h [RISCV] Add a really basic cost model for SK_Splice. 2022-02-09 11:43:31 -08:00